Binary Adders - GATE ECE Engineering (ECE) Digital Circuits Free MCQ Test

Test: Binary Adders - Question 1

In which of the following adder circuits, the carry look ripple delay is eliminated?

A.
Half adder
B.
Full adder
C.
Parallel adder
D.
Carry-look ahead adder

Detailed Solution: Question 1

Concept:

Carry Lookahead adder:

A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic.

A carry-look ahead adder improves speed by reducing the amount of time required to determine to carry bits.

It calculates one or more carries before the sum, which reduces the wait time/Ripple delay to calculate the result of the larger value bits of the adder.

The 4-bit carry look-ahead carry adder is shown in the figure given below.

Test: Binary Adders - Question 2

For an n-bit binary adder, what is the number of gates through which a carry has to propagate from input to output?

A.
n
B.
2ⁿ
C.
n²
D.
n + 1

Detailed Solution: Question 2

Binary full adder circuit is as shown:

To add two one-bit numbers, along with carrying bit, only two gates are required to propagate carry from input to output.

Therefore, for an n-bit binary adder, 2n number of gates through which a carry has to propagate from input to output.

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*Answer can only contain numeric values

Test: Binary Adders - Question 3

A serial adder is operating with a clock frequency of 10 MHz. Time required to sum 1010111 and 10111 number is –(in μsec)

Detailed Solution: Question 3

Total time of addition of a serial adder depends only on the number which has more number of bits. Here in this addition one no. contains 7 bits and another one 5 bits. So 7 clock periods are required to add the two numbers.

Total time =

*Answer can only contain numeric values

Test: Binary Adders - Question 4

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.

Detailed Solution: Question 4

C₁₄ will be available after 12 x 15 = 180 n sec.

The FA₁₅ adder will take 12 nsec to generate the carry C₁₅and 15 nsec to generate the sum S₁₅ after 180 nsec.

So, the worst-case delay is (180 n sec + 15 n sec) = 195 nsec

Test: Binary Adders - Question 5

Four different types of Adders are used to construct an 8-bit adder. The characteristic of each full adder in terms of delay is as follows:

The structure of the FA is as follows:

The maximum no of addition per second that the above adder can perform is –

A.
3.23 x 10⁶
B.
5 x 10⁶
C.
5.23 x 10⁶
D.
5.95 x 10⁶

Detailed Solution: Question 5

The carry generation timings are as follows:

T(C₁) = 18 nsec

T(C₂) = (18 + 27) nsec = 45 nsec

T(C₃) = (23 + 45) nsec = 68 nsec

T(C₄) = (32 + 68) nsec = 100 nsec

T(C₅) = (18 + 100) nsec = 118 nsec

T(C₆) = (23 + 118) nsec = 141 nsec

T(C₇) = (27+141) nsec = 168 nsec

C_out = (32 + 168) nsec = 200 nsec

To find the maximum no of addition we have to find the time taken for each addition

Now, sum generation times are as follows:

T(S₈) = (168 + 23) nsec = 191 nsec

T(S₇) = (141 + 169) nsec = 310 nsec

T(S₆) = (118 + 72) nsec = 190 nsec

We see that S₇ appears at t = 310 nsec while the last carry C_out appears before at t = 200 nsec.

As, S₇ takes the longest time to generate the output.

Thus, the maximum number of addition per second

*Answer can only contain numeric values

Test: Binary Adders - Question 6

Consider a 4 bit ripple carry adder. Each full adder is implemented using a 3 input exor gate, three 2 input AND gates and one 3 input or gate. Consider the delay of 3 input exor gate to be 3 n-sec, the delay of each 2 input AND gate to be 1 nsec and the delay of each 3 input or gate to be 1 nsec. The total time taken by the 4 bit ripple carry adder to perform successful addition operation is ________.

Detailed Solution: Question 6

Concept:

The implementation of circuit is shown

To generate S₁ [C₀, A₁, B₁ are required]

To generate C₁ [C₀, A₁, B₁ are required]

To generate S₂ [C₁, A₂, B₂ are required]

To generate C₂ [C₁, A₂, B₂ are required]

Calculation:

Different output and time after which they are generated are:

Test: Binary Adders - Question 7

Let x be the number of AND gates present in the 4 bit carry look ahead adder and y be the number of OR gates presents in that adder then the value of 2x + 2y is ____________

A.
18
B.
36
C.
14
D.
28

Detailed Solution: Question 7

AND gates = n(n + 1)/2

OR gates = n

So AND gates = 10

OR gates = 4

So 2x + 2y = 28

Test: Binary Adders - Question 8

3 bits full adder contains ____________

A.
3 combinational inputs
B.
4 combinational inputs
C.
6 combinational inputs
D.
8 combinational inputs

Detailed Solution: Question 8

3 bits full adder contains 2³ = 8 combinational inputs.

Test: Binary Adders - Question 9

The number of logic gates and the way of their interconnections can be classified as ____________

A.
Logical network
B.
System network
C.
Circuit network
D.
Gate network

Detailed Solution: Question 9

The number of different levels of logic gates is represented in a fashion which is known as a logical network.

Test: Binary Adders - Question 10

The output sum of two decimal digits can be represented in ____________

A.
Gray Code
B.
Excess-3
C.
BCD
D.
Hexadecimal

Detailed Solution: Question 10

The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.

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Binary Adders - Free MCQ Practice Test with solutions, GATE ECE Engineering

MCQ Practice Test & Solutions: Test: Binary Adders (10 Questions)

In which of the following adder circuits, the carry look ripple delay is eliminated?

For an n-bit binary adder, what is the number of gates through which a carry has to propagate from input to output?

A serial adder is operating with a clock frequency of 10 MHz. Time required to sum 1010111 and 10111 number is –(in μsec)

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.

Four different types of Adders are used to construct an 8-bit adder. The characteristic of each full adder in terms of delay is as follows:

The structure of the FA is as follows:

The maximum no of addition per second that the above adder can perform is –

Let x be the number of AND gates present in the 4 bit carry look ahead adder and y be the number of OR gates presents in that adder then the value of 2x + 2y is ____________

3 bits full adder contains ____________

The number of logic gates and the way of their interconnections can be classified as ____________

The output sum of two decimal digits can be represented in ____________

Digital Circuits

Digital Circuits

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Binary Adders - Free MCQ Practice Test with solutions, GATE ECE Engineering

MCQ Practice Test & Solutions: Test: Binary Adders (10 Questions)

In which of the following adder circuits, the carry look ripple delay is eliminated?

For an n-bit binary adder, what is the number of gates through which a carry has to propagate from input to output?

A serial adder is operating with a clock frequency of 10 MHz. Time required to sum 1010111 and 10111 number is –(in μsec)

A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum-propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________.

Four different types of Adders are used to construct an 8-bit adder. The characteristic of each full adder in terms of delay is as follows: The structure of the FA is as follows: The maximum no of addition per second that the above adder can perform is –

Let x be the number of AND gates present in the 4 bit carry look ahead adder and y be the number of OR gates presents in that adder then the value of 2x + 2y is ____________

3 bits full adder contains ____________

The number of logic gates and the way of their interconnections can be classified as ____________

The output sum of two decimal digits can be represented in ____________

Digital Circuits

Digital Circuits

Top Courses for Electronics and Communication Engineering (ECE)

About this Electronics and Communication Engineering (ECE) Practice Test

Explore more Electronics and Communication Engineering (ECE) Study Resources

Four different types of Adders are used to construct an 8-bit adder. The characteristic of each full adder in terms of delay is as follows:

The structure of the FA is as follows:

The maximum no of addition per second that the above adder can perform is –