Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Tests > Computer Architecture & Organisation (CAO) > Test: Cache Miss & Hit - Computer Science Engineering (CSE) MCQ
Test: Cache Miss & Hit - Computer Science Engineering (CSE) MCQ
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10 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Cache Miss & Hit
Test: Cache Miss & Hit for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Cache Miss & Hit questions and answers have been
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Test: Cache Miss & Hit - Question 1
The main memory is structured into modules each with its own address register called ______
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Test: Cache Miss & Hit - Question 2
When consecutive memory locations are accessed only one module is accessed at a time.
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Test: Cache Miss & Hit - Question 3
In memory interleaving, the lower order bits of the address is used to
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Test: Cache Miss & Hit - Question 4
The number successful accesses to memory stated as a fraction is called as _____
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Test: Cache Miss & Hit - Question 5
The number failed attempts to access memory, stated in the form of fraction is called as _________
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Test: Cache Miss & Hit - Question 6
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.
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Test: Cache Miss & Hit - Question 7
In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______
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Test: Cache Miss & Hit - Question 8
If hit rates are well below 0.9, then they’re called as speedy computers.
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Test: Cache Miss & Hit - Question 9
The extra time needed to bring the data into memory in case of a miss is called as _____
Test: Cache Miss & Hit - Question 10
The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
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