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Test: D Flip Flop - Electronics and Communication Engineering (ECE) MCQ


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15 Questions MCQ Test Digital Circuits - Test: D Flip Flop

Test: D Flip Flop for Electronics and Communication Engineering (ECE) 2024 is part of Digital Circuits preparation. The Test: D Flip Flop questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The Test: D Flip Flop MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: D Flip Flop below.
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Test: D Flip Flop - Question 1

Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?

Detailed Solution for Test: D Flip Flop - Question 1

Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.

Test: D Flip Flop - Question 2

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

Detailed Solution for Test: D Flip Flop - Question 2

PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.

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Test: D Flip Flop - Question 3

Which of the following is correct for a D latch?

Detailed Solution for Test: D Flip Flop - Question 3

If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. It stores the value on the data line.

Test: D Flip Flop - Question 4

Which of the following is correct for a gated D flip-flop?

Detailed Solution for Test: D Flip Flop - Question 4

If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the value on the data line.

Test: D Flip Flop - Question 5

In D flip-flop, if clock input is HIGH & D=1, then output is ___________

Detailed Solution for Test: D Flip Flop - Question 5

If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram:

Test: D Flip Flop - Question 6

A D flip-flop can be constructed from an ______ flip-flop.

Detailed Solution for Test: D Flip Flop - Question 6

A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.

Test: D Flip Flop - Question 7

The D flip-flop has _______ input.

Detailed Solution for Test: D Flip Flop - Question 7

The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

Test: D Flip Flop - Question 8

The characteristic equation of D-flip-flop implies that ___________

Detailed Solution for Test: D Flip Flop - Question 8

A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is independent of the present state.

Test: D Flip Flop - Question 9

A positive edge-triggered D flip-flop will store a 1 when ________

Detailed Solution for Test: D Flip Flop - Question 9

A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.

Test: D Flip Flop - Question 10

Which of the following describes the operation of a positive edge-triggered D flip-flop?

Detailed Solution for Test: D Flip Flop - Question 10

Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.

Test: D Flip Flop - Question 11

With regard to a D latch ________

Detailed Solution for Test: D Flip Flop - Question 11

Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input. It stores the value on the data line.

Test: D Flip Flop - Question 12

Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

Detailed Solution for Test: D Flip Flop - Question 12

By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

Test: D Flip Flop - Question 13

In D flip-flop, if clock input is LOW, the D input ___________

Detailed Solution for Test: D Flip Flop - Question 13

In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.

Test: D Flip Flop - Question 14

The D flip-flop has ______ output/outputs.

Detailed Solution for Test: D Flip Flop - Question 14

The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

Test: D Flip Flop - Question 15

In D flip-flop, D stands for _____________

Detailed Solution for Test: D Flip Flop - Question 15

The D of D-flip-flop stands for “data”. It stores the value on the data line.

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