Test: DRAM Interfaces - Computer Science Engineering (CSE) MCQ

Explanation: In the basic DRAM interfacing, the higher order bits asserts the RAS signal and the lower order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the processor.

Explanation: The memory refresh is performed every 15 microseconds in order to remain compatible.

Explanation: The direct method access limits the wait state-free operation which lowers the processor speed.

Explanation: EDO RAM is a special kind of random access memory which can improve the time to read from the memory on faster microprocessors. The example of such a microprocessor is Intel Pentium.

Explanation: Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.

Explanation: The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses RAM controller, a bus which connects the microprocessor and the device, and a random access memory.

Explanation: The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.

Explanation: In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.

Explanation: The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

Explanation: The page mode operation have memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is an access outside the page boundary and two or more wait states.

Explanation: The accessing of data outside the page boundary can cause missing of pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

Explanation: Extended data out memory is a fast page mode RAM which has a faster cycling process which makes EDO memory a faster page mode access.

Explanation: The page mode, nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for fast static RAMs.

Explanation: The EDO DRAM is also known as hyper page mode enable DRAM because of the faster page mode operation along with some additional features.

Explanation: The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.