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Test: Flip Flops - Electronics and Communication Engineering (ECE) MCQ


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10 Questions MCQ Test Digital Electronics - Test: Flip Flops

Test: Flip Flops for Electronics and Communication Engineering (ECE) 2024 is part of Digital Electronics preparation. The Test: Flip Flops questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The Test: Flip Flops MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Flip Flops below.
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Test: Flip Flops - Question 1

A modulo - 272 counter requires the following number of flip-flops: 

Detailed Solution for Test: Flip Flops - Question 1

We can design a Modulo 2n counter with n flip-flops. We need a little more because 272 is greater than 256, i.e. 28; 29 = 512, which is greater than 272. In order to create a Modulo 272 counter, only 9 flip-flops are required. Option (B) is the right answer.

Test: Flip Flops - Question 2

Take a look at the following assertions about counters:

S1: An Overbeck counter has a Hamming distance of 1 and a Johnson counter has a Hamming distance of 2.
S2: In the Overbeck counter, only output sequences 0, 8, 12, 14, 15, 7, 3, 1, 0,... are feasible, but output sequences 2, 1, 8, 4, 2, 1,... are not.
S3: A binary counter may represent 2N states, where N is the number of bits in the code, whereas an Overbeck counter and a Johnson counter can only represent N and 2N states, respectively.

Detailed Solution for Test: Flip Flops - Question 2

The following are correct statements: S1: An Overbeck counter has a Hamming distance of 2 while a Johnson counter has a Hamming distance of 1. S2: In the Johnson counter, output sequences of 0, 8, 12, 14, 15, 7, 3, 1, 0,... are feasible, but in the Overbeck counter, output sequences of 2, 1, 8, 4, 2, 1,... are possible. S3: A binary counter may represent 2N states, where N is the number of bits in the code, but an Overbeck counter and a Johnson counter can only represent N states and 2N states, respectively.

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Test: Flip Flops - Question 3

If both S and R inputs of an SR latch formed by cross-coupling two NAND gates are set to 0, the output is

Detailed Solution for Test: Flip Flops - Question 3

We get both Q and Q' as 1 when both R and S are set to 0. This output will be permanent, and it will not be affected by the sequence in which the events occur; it will only be affected by the input values [NO RACE CONDITION]. However, if we change R=S=1 after this state, the output would be indeterminate depending on which NAND gate processes first (either Q or Q' will become 0, but we can't tell which [RACE CONDITION]), resulting in an indeterminate state.

Test: Flip Flops - Question 4

In an RS flip-flop, if the S line (Set line) is set high (1) and the R line  is set low (0), then the state of the flip-flop is

Detailed Solution for Test: Flip Flops - Question 4

When the Set line is set high, and the Reset line is set low, then the RS flip-flop has the state set to 1. 

Test: Flip Flops - Question 5

A modulus -12 ring counter requires a minimum of

Detailed Solution for Test: Flip Flops - Question 5

A ring counter requires 'n' flip-flops for 'n' number of states. A modulus-12  has 12 states starting from 0000 to 1011. At least 12-bits are required to design a modulus-12 counter.  

Test: Flip Flops - Question 6

Which of the following option input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?

Detailed Solution for Test: Flip Flops - Question 6

RS flip flop using NAND gates. So, 00 input causes an indeterminate state which MAY lead to oscillation.

Test: Flip Flops - Question 7

To design a synchronous counter having sequence ( 0-1-0-2-0-3 ) and then repeats. To implement this counter is the minimum number of J-K flip-flops required. Note: This question was asked as a Numerical Answer Type.

Detailed Solution for Test: Flip Flops - Question 7

Total 4. 2 J-K flip-flops for synchronous counter + 2 J-K flip-flops to make 2 bit counter. Actually, when we have repeated again, then after three, we don't know that our Synchronous counter will go to which zero. To make it work right, we need to move it to 1st zero after 3 2nd zero after 1 3rd zero after 2 i.e. 0 -> 1 -> 0 -> 2 -> 0 -> 3 (from here it again go to 1st zero). In order to decide which zero to move on, we use counters from 1 to 3; I have attached the truth table of a normal 2 bit synchronous counter using JK flip flop.

Test: Flip Flops - Question 8

The minimum number of J K flip-flops required to construct a synchronous counter with the sequence like (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is:- 

Detailed Solution for Test: Flip Flops - Question 8

Count sequence is 00, 00, 01, 01, 10, 10, 11, 11 the  repeated sequence is above present. As two bits will not be sufficient, we need at least three flip-flops. So, the answer is 3.

Test: Flip Flops - Question 9

A four-bit Johnson counter with an initial value of (0000). The sequence of counting is:-

Detailed Solution for Test: Flip Flops - Question 9

The 4 bit Johnson counter connects the complement of the output of the last shift register with the input of the first register with shift distance=1, i.e., 1 bit will shift/cycle. It work as follows:- 0000 //The last 0 complemented & fed as input to first register = ( 1000 1100 1110 1111 )//The last one complimented & fed as input to first register = ( 0111 0011 0001 0000).

Test: Flip Flops - Question 10

A positive edge-triggered D flip-flop is connected to a positive edge-triggered J K flip-flop. The Q output of the D flip-flop is connected to both the J and K inputs of the J K flip-flop, while the Q output of the J K flip-flop is connected to the input of the D flip-flop. At first, the output of a D flip-flop is set to logic one, and the output of the JK flip-flop is cleared. Which one of the following options is the bit sequence generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running standard clock? Consider that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

Detailed Solution for Test: Flip Flops - Question 10

At first, the Q output of D - FF = 1 in starting Q output of J K - F F = 0. Now with the help of the present state and next state, the circuit.

  • Toggle: J = K = 1
  • Hold : J = K = 0

Make table Q output of D-FF is going to next state input of J K-F F and the bits sequence produced is like 110110…..Including initial condition (0), we get output as 0110110110. Hence answer is (A) part.

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