Test: Microprocessor Interfacing - Electronics and Communication Engineering (ECE) MCQ

Size of memory= 8 K bytes
= 8 x 1024 x 8 bits
= 213 x 8 bits
= 2n x m bits
Here, n = No. of address lines = 13
and m = No. of data lines = 8

Size of given chip
= 1 K x 4 bits
= 1024 x 4 bits

Size of required memory bank
= 16 K x 8 bits
= 16 x 1024 x 8 bits

Required number of memory chips

An 8085 microprocessor has 16 address lines and 8 data lines. Thus, it can address maximum of 216 I/O devices and memory.

For chip select  signal to be low, we have: 

The address range with this combination will be as follows:

In an 8085 microprocessor, the I/O devices can be used is a memory mapped I/O only. An 8085 microprocessor is an 8 – bit microprocessor that is designed by the Intel in 1977 using the NMOS technology.  This 8085 microprocessor has an 8 – bit data bus, a 16 – bit address bus, a 16 – bit program counter, a 16 – bit stack pointer, Six 8-bit registers arranged in pairs like BC, DE, HL. This processor is usually found in mobile phones, washing machines, microwave ovens.

Size of the given memory chip = 64 x 8 bits = 2⁶ x 8 bits = 2n x m bits

Here, n = 6 and m - 8
Hence, the chip has 6 address lines and 8 data lines.
Now, when eight memory chips of size 26 x 8 bits have their address buses connected together, then the address lines will be same but data lines will become 8 x 8 = 64. Thus, the size of the resultant memory will be 64 x 64 bits

Statement-3 is not correct because in memory mapped I/O scheme of communication with microprocessor, the processor manipulates ‘ registers with same instruction that are used to manipulate memory locations.

One memory location of an 8-bit microcontroller external RAM will store 8 bits of data or 1 byte. The number of memory locations in the memory range from 8000 H to 9FFF H are equal to (9FFF - 8000)_H + 1 = 2000 H.
Hence, the number of bytes the memory locations from 8000 H to 9FFF H can store is equal to 2000 H or 8192.

For 4 K RAM (4 x 1024 = 2¹²), the number of address lines required will be 12. Hence, out of the 16 address'lines, 12 addresses lines (i.e. A₁₁., to A₀) will be used for addressing the memory location in a chip and the remaining four (i.e. A₁₅ to A₁₂) will be used for selecting the chip. Thus, the chip select signal is CS =  .  So, the address lines A₁₅ = 0, A₁₄ = 1 and A₁₃ = 1. The line A₁₂ may be 0 or 1 and hence we will get separate range corresponding to A₁₂ = 1 and A₁₂ = 0