Test: Sequential Circuits- 2 - Computer Science Engineering (CSE) MCQ

​Consider the circuit given below with initial state Q₀ = 1; Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀ 

Which one of the following is the. correct state sequence of the circuit?

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit 

Which one of the following is TRUE?

Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q₀Q₁ Let the initial state be 00. The state transition sequence is:

The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop

The number of flip-flops required in a modulo N counter is

Consider the figure given below:

​Initially all flip-flops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?

​The logic circuit shown below is a 3-bit

The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will

Consider the following control circuit which contains a 3-bit register and a black box with some combinational logic

The initial state of the circuit is Q₁ Q₂ Q₃ = 000.
The circuit generates the control sequence.
(010) → ( 110) → ( 001) →(001) → . . . → ( 001)
On successive clock cycles. Which of the following sets of equations are implemented by the combinational logic in the black box?

‘n’ flip-flop will divide the clock frequency by a factor of

Let a_n a_n-1 ... a₁ a₀ be the binary representation of an integer b. The integer b is divisible by 3 if

If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by