Test: Shift Registers - 2 - Electrical Engineering (EE) MCQ

Concept: In serial IN/Parallel out shift register data will be shifted all at a time with every clock pulse.

since initially 1111 stored

so after 3^rd clock pulse output will be 0101

This is represented when the process has the clock signal in its sensitivity list else we can’t call that a sequential circuit.

This is represented when the process has the clock signal in its sensitivity list else we can’t call that a sequential circuit.

Analysis:

The code in the, begin and end block has two assignments.

temp(0) <= sin;

This stamen represents that the assignment of the input bit to the temp signal at the first location since the temp signal is 8 bit.

The FOR loop represents that each previous value is shifted to the next location and it will do for the 7 times whenever the loop executes. The statement responsible for this is:

temp(i + 1) <= temp(i);

if i = 0, then i(1) will have the same value as of i(0).

If i = 1, then i(2) will have the same value as i(1).

In this way, the iteration will be completed and this structure represents the SISO register where the input is shifted serially and output is also taken serially.

sout <= temp(7);

This statement represents that the output is taken serially.

Simple example of 4 bit is shown below:

Concept:

An n-bit serial in serial out register using D flip flops is as shown:

For an n-bit shift register, we require n D flip flops.

Let the propagation delay of a single D flip flop = t ns.

Propagation delay for the n bit SISO (serial in serial out) shift register will be:

tpd= (n × t) ns 

Calculation:

Given:

n = 8

f = 4 MHz

t = 1 f = 1/4

t = 0.25 μs (for one flip flop)

For 8 flip flops

t_pd = 8 × 0.25 μs

t_pd = 2 μs

Hence option (4) is the correct answer.

To carry out multiple shift operations in a single clock cycle, parallel shift registers are used.

This is explained with the help of the PISO shift register where the data is simultaneously placed in all the registers in a single clock cycle with multiple shifts taking place.

Parallel-in-serial out (PISO):

The parallel data is loaded into register simultaneously and is shifted out of the register serially, one bit at a time, under clock control.

The basic block diagram is as shown:

The data is loaded into the register simultaneously through the registers P₃ to P₀ at clock pulse and no clock is required to load the inputs. The data is then read out sequentially in normal shift right mode in ‘Q’.

The register is given serial input with serial data 1100, the shift register is initially cleared 0000. 

Since we have to store 1100 in the register, bits will be entered from the right. 

The contents of the register after 1st pulse 0000.

Similarly, after the second shift, the contents of the register are 0000. 

After the third clock pulse, the contents will be 1000

and after the fourth clock pulse, the contents will be 1100

Truth table of X-OR gate:

Analysis:

X = D₁ ⊕ D₀

D₃⁺ = X ⊕ D₂

D₂⁺ = D₃

D₁⁺ = D₂

D₀⁺ = D₁

Concept:

The data movement from left to right is shown in the below figure:

The structure of the SIPO register is:

Basic data movement in a shift register is shown below:

Calculation

Given that the initial content is 0000 and the data is 1101.

After the first clock pulse, the value of the register is 1000.

After the second clock pulse, the value of the register is 0100.

After the third clock pulse, the value of the register is 1010.

After the fourth clock pulse, the value of the register is 1101.

All are the type of Shift Operation therefore option 1 is correct, that is, All of the Options

Logical Shift Left

One position moves each bit to the left one by one

Logical Shift Right

One position moves each bit to the right one by one

Left Arithmetic Shift

One position moves each bit to the left one by one. The empty least significant bit (LSB) is filled with zero and the most significant bit (MSB) is rejected.

Right Arithmetic Shift
One position moves each bit to the right one by one and the least significant bit is rejected and the empty MSB is filled with the value of the previous MSB.

Circular shift

The circular shift circulates the bits in the sequence of the register around both ends without any loss of information.

Shift Register: 

1). A shift register has the capability to store one bit and if another bit is to store, in such a situation it deletes the previous data and stores them.

2). A universal shift register is a bidirectional register whose inputs can be either in serial form or in parallel form. (Option 1 is true)

3). An n-bit shift register consists of ‘N’ number of D flipflops and ‘N’ number of MUX.(Option 3 is correct)

4). The universal shift register has a clear control that clears the contents of the register to 0 and a preset control to set the contents of the register to 1. (Option 4 is correct)

5). The universal shift register does not have an internal clock to synchronize the operations (Option 2 is false)

The basic block diagram of a shift register is as shown:

Input to A is Exor of Previous value of A and D

New Input to B , C, D are previous values of A, B, C respectively.

Total clock cycles required is 10