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Test: Shift Registers - Electronics and Communication Engineering (ECE) MCQ


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10 Questions MCQ Test Digital Circuits - Test: Shift Registers

Test: Shift Registers for Electronics and Communication Engineering (ECE) 2024 is part of Digital Circuits preparation. The Test: Shift Registers questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The Test: Shift Registers MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Shift Registers below.
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Test: Shift Registers - Question 1

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________

Detailed Solution for Test: Shift Registers - Question 1

One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit information of 8 bits.

Test: Shift Registers - Question 2

A 4-bit serial-in parallel-out shift register is initially set to 1111. The data 1010 is applied to the input. After 3 clock cycles the output will be:

Detailed Solution for Test: Shift Registers - Question 2

Concept: A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit. The output from each flip-Flop is connected to the D input of the flip-flop at its right. Shift registers hold the data in their memory which is moved or “shifted” to their required positions on each clock pulse.

Calculation: If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs QA to QD after the fourth clock pulse.

After 3 clock cycles, the output will be 0101

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Test: Shift Registers - Question 3

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

Detailed Solution for Test: Shift Registers - Question 3

LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.

Test: Shift Registers - Question 4

How can parallel data be taken out of a shift register simultaneously?

Detailed Solution for Test: Shift Registers - Question 4

Because no other flip-flops are connected with the output Q, therefore one can use the Q out of each FF to take out parallel data.

Test: Shift Registers - Question 5

The full form of SIPO is ___________

Detailed Solution for Test: Shift Registers - Question 5

SIPO is always known as Serial-in Parallel-out.

Test: Shift Registers - Question 6

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

Detailed Solution for Test: Shift Registers - Question 6

f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-sec.

Test: Shift Registers - Question 7

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

Detailed Solution for Test: Shift Registers - Question 7

In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

Test: Shift Registers - Question 8

What is meant by the parallel load of a shift register?

Detailed Solution for Test: Shift Registers - Question 8

At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.

Test: Shift Registers - Question 9

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?

Detailed Solution for Test: Shift Registers - Question 9

A shift register can shift it’s data either left or right. The universal shift register is capable of shifting data left, right and parallel load capabilities.

Test: Shift Registers - Question 10

Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.

Detailed Solution for Test: Shift Registers - Question 10

The registers in which data can be shifted serially or parallelly are known as shift registers. Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).

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