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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Computer Architecture & Organisation (CAO)  >  Test: Static & Large Memories - Computer Science Engineering (CSE) MCQ

Test: Static & Large Memories - Computer Science Engineering (CSE) MCQ


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25 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Static & Large Memories

Test: Static & Large Memories for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Static & Large Memories questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Static & Large Memories MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Static & Large Memories below.
Solutions of Test: Static & Large Memories questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: Static & Large Memories solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Static & Large Memories | 25 questions in 15 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Static & Large Memories - Question 1
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The duration between the read and the mfc signal is ______

Detailed Solution for Test: Static & Large Memories - Question 1

Answer: a
Explanation: The time between the issue of read signal and the completion of it is called memory access time.

Test: Static & Large Memories - Question 2
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 The minimum time delay between two successive memory read operations is ______

Detailed Solution for Test: Static & Large Memories - Question 2

Answer: a
Explanation: The Time taken by the cpu to end one read operation and to start one more is cycle time.

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Test: Static & Large Memories - Question 3
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MFC is used to _________

Detailed Solution for Test: Static & Large Memories - Question 3

Answer: c
Explanation: The MFC stands for memory Function Complete.

Test: Static & Large Memories - Question 4
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__________ is the bootleneck, when it comes computer performance.
Detailed Solution for Test: Static & Large Memories - Question 4

Answer: b
Explanation: The processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance.

Test: Static & Large Memories - Question 5
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The logical addresses generated by the cpu are mapped onto physical memory by ____
Detailed Solution for Test: Static & Large Memories - Question 5

Answer: c
Explanation: The MMU stands for memory management unit, which is used to map logical address onto phsical address.

Test: Static & Large Memories - Question 6
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VLSI stands for ___________
Test: Static & Large Memories - Question 7
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The cells in a row are connected to a common line called ______
Detailed Solution for Test: Static & Large Memories - Question 7

Answer: b
Explanation: This means that the cell contents together form one word of instruction or data.

Test: Static & Large Memories - Question 8
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 The cells in each column are connected to ______
Detailed Solution for Test: Static & Large Memories - Question 8

Answer: d
Explanation: The cells in each column are connected to the sense/write circuit using two bit lines and which is inturn connected to the data lines.

Test: Static & Large Memories - Question 9
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The word line is driven by the _____
Test: Static & Large Memories - Question 10
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A 16 X 8 organisation of memory cells, can store upto _____
Detailed Solution for Test: Static & Large Memories - Question 10

Answer: d
Explanation: It can store upto 128 bits as each cell can hold one bit of data.

Test: Static & Large Memories - Question 11
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A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into _____
Detailed Solution for Test: Static & Large Memories - Question 11

Answer: d
Explanation: All the others require less than 10 address bits.

Test: Static & Large Memories - Question 12
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Circuits that can hold their state as long as power is applied is _______
Test: Static & Large Memories - Question 13
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The number of external connections required in 16 X 8 memory organisation is _____
Detailed Solution for Test: Static & Large Memories - Question 13

Answer: a
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.

Test: Static & Large Memories - Question 14
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 The advantage of CMOS SRAM over the transistor one’s is _________
Detailed Solution for Test: Static & Large Memories - Question 14

Answer: d
Explanation: This is because the cell consumes power only when it is being accessed.

Test: Static & Large Memories - Question 15
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 In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
Detailed Solution for Test: Static & Large Memories - Question 15

Answer: c
Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation).

Test: Static & Large Memories - Question 16
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 The chip can be disabled or cut off from external connection using ______
Detailed Solution for Test: Static & Large Memories - Question 16

Answer: a
Explanation: The chip gets enabled if the CS is set otherwise the chip gets disabled.

Test: Static & Large Memories - Question 17
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To organise large memory chips we make use of ______
Detailed Solution for Test: Static & Large Memories - Question 17

Answer: c
Explanation: The cell blocks are arranged and put in a memory module.

Test: Static & Large Memories - Question 18
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The less space consideration as lead to the development of ________ (for large memories).
Detailed Solution for Test: Static & Large Memories - Question 18

Answer: d
Explanation: The SIMM (single inline memory module) or DIMM (dual inline memory module) occupy less space while providing greater memory space.

Test: Static & Large Memories - Question 19
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The SRAM’s are basically used as ______
Detailed Solution for Test: Static & Large Memories - Question 19

Answer: b
Explanation: The SRAM’s are used as caches as their opeartion speed is very high.

Test: Static & Large Memories - Question 20
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The higher order bits of the address are used to _____
Test: Static & Large Memories - Question 21
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The address lines multiplexing is done using ______
Detailed Solution for Test: Static & Large Memories - Question 21

Answer: b
Explanation: This unit multiplexes the various address lines to lesser pins on the chip.

Test: Static & Large Memories - Question 22
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The controller multiplexes the addresses after getting the _____ signal.
Detailed Solution for Test: Static & Large Memories - Question 22

Answer: d
Explanation: The controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.

Test: Static & Large Memories - Question 23
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The RAS and CAS signals are provided by the ______
Detailed Solution for Test: Static & Large Memories - Question 23

Answer: c
Explanation: The multiplexed signal of the controller is split into RAS and CAS.

Test: Static & Large Memories - Question 24
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Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ______
Detailed Solution for Test: Static & Large Memories - Question 24

Answer: b
Explanation: The refresh overhead is calculated by taking into account the total time for refreshing and the interval of each refresh.

Test: Static & Large Memories - Question 25
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 When DRAM’s are used to build a complex large memory,then the controller only provides the refresh counter. 
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