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Gate Practice Test: Electrical Engineering(EE)- 11 - Electrical Engineering (EE) MCQ


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30 Questions MCQ Test - Gate Practice Test: Electrical Engineering(EE)- 11

Gate Practice Test: Electrical Engineering(EE)- 11 for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Gate Practice Test: Electrical Engineering(EE)- 11 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Gate Practice Test: Electrical Engineering(EE)- 11 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Gate Practice Test: Electrical Engineering(EE)- 11 below.
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Gate Practice Test: Electrical Engineering(EE)- 11 - Question 1

Statement: All bags are cakes. All lamps are cakes.
Conclusions:
I. Some lamps are bags.
II. No lamp is bag.
Deduce which of the above conclusion logically follows statements:

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 1

Conclusion I and II are complementary. So either conclusion I or conclusion II follows the statement.

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 2

Man does not live by __________ alone.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 2

Man does not live by bread alone

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Gate Practice Test: Electrical Engineering(EE)- 11 - Question 3

Extreme focus on syllabus and studying for tests has become such a dominant concern of Indian students that they close their minds to anything __________ to the requirements of the exam.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 3

Extraneous – irrelevant or unrelated to the subject being dealt with

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 4

Select the pair that best expresses a relationship similar to that expressed in the pair
LIGHT : BLIND

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 5

If = log(a + b), then:

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 5

RHS : Log a + Log b = Log ab

For LHS : Log a/b + Log b/a

              = Log ((a/b) *(b/a))

              =Log (ab/ab) =1

LHS = RHS

∴1=a+b

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 6

In an exam, the average was found to be 50 marks. After deducting computational errors the marks of the 100 candidates had to be changed from 90 to 60 each and average came down to 45 marks. Total number of candidates who took the exam was:

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 6

Let number of candidates be n

n = 600

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 7

A solid 4cm cube of wood is coated with red paint on all the six sides. Then the cube is cut into smaller 1cm cubes. How many of these 1cm cubes have no colour on any side?

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 7

Number of cubes with 3 faces red = 8
Number of cubes with 2 faces red = 24
Number of cubes with 1 face red = 24
Number of cubes with no face red = 64-(24+24+8) = 8

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 8

One of the warmest winters on record has put consumers in the mood to spend money. Spending is to be the strongest in thirteen years. During the month of February, sales of existing single family homes hit an annual record rate of 4.75 million. This paragraph best supports the statement that:

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 9

The age of father is 4 times more than the age of his son Amit. After 8 years, he would be 3 times older than Amit. After further 8 years, how many times will he be older than Amit?

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 9

Let Amit’s age be n years
Age of his father = (4*n) = 4n years
After 8 years:
Amit’s age = n + 8
Father’s age =
3(n + 8) = 4n + 8
3n + 24 = 4n + 8
16 = n
n = 16 years
After further 8 years:
Amit’s age = 24 years
Father’s age = 4n +16 = 80 years
So father is 2.5 times older than Amit.

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 10

Pipe A, B and C are kept open and together fill a tank in t minutes. Pipe A is kept open throughout, pipe B is kept open for the first 10 minutes and then closed. Two minutes after pipe B is closed, pipe C is opened and is kept open till the tank is full. Each pipe fills an equal share of the tank. Furthermore, it is known that if pipe A and B are kept open continuously, the tank would be filled completely in t minutes. Find t?

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 10

A is kept open for all t minutes and fills one-third the tank. Or, A should be able to fill the entire tank in '3t' minutes.

A and B together can fill the tank completely in t minutes. A alone can fill it in 3t minutes.

A and B together can fill 1/t  of the tank in a minute. A alone can fill 1/3t of the tank in a minute. So, in a minute, B can fill 1/t - 1/3t=2/3t. Or, B takes 3t/2 minutes to fill an entire tank. 

To fill one-third the tank, B will take t/2 minutes. B is kept open for t -10 minutes.

   t/2 =  t - 10,

∴ t = 20 minutes.

A takes 60 minutes to fill the entire tank, B takes 30 minutes to fill the entire tank. A is kept open for all 20 minutes. B is kept open for 10 minutes.
C, which is kept open for 8 minutes also fills one-third the tank. Or, C alone can fill the tank in 24 minutes.

*Answer can only contain numeric values
Gate Practice Test: Electrical Engineering(EE)- 11 - Question 11

The value of ‘V’ from the given below circuits is_____________ volts.


Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 11

By redrawing the given circuit

Current flowing through 30Ω is zero. So circuits becomes

Current flowing through 10Ω resistor is

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 12

For eliminating Harmonics from the emf generated the coil span must be.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 12


, Full pitch

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 13

Determine the value of

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 13

Let x=2t
      t=x/2
     dt=dx/2
∴ Integral becomes

   = sin(x/2) * δ(x-(pie/2)) * (dx/2)
∴ (1/2) *sin(pie/4) =1/(2√2)

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 14

In HVDC converter stations equipment using thyristor it is necessary to use a large number of thyristors in series because

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 15

The holding current of a SCR is 18mA. Its latching current will be

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 15

Ratio between latching current to  holding current is 2-3 times.

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 16

In a 132 kV system, the phase to ground capacitance is 0.01 µF and the inductance is 4H. Calculate the voltage appearing across the electrodes of C.B. If a magnetizing current at 5 amp is interrupted. Calculate the critical resistance to be connected, to eliminate restriking.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 16

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 17

A phase lead compensating network has its transfer function The maximum phase lead occurs at a frequency of:

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 17

Comparing with the standard phase lead compensating network,

So, maximum phase lead occurs at frequency


= 50 rad /sec

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 18

The time taken for the output to settle within 2% of step input for the control system represented by  is given by

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 18

Comparing the above transfer function with the standard second order transfer function.


Settling time for 2% tolerance band =
= = 1.6 sec

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 19

When 30V dc is applied to the vertical deflection plates of CRO, the bright spot moves 1cm away from the center if 30V (rms) is applied then the picture on screen

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 20

A compound dc generator is delivering full load current at a terminal voltage of 230V. It’s
series field winding get’s short circuit. If it’s terminal voltage becomes.
1. More than 230V it is over compounded
2. More than 230V it is differential compound
3. Less than 230V it is over compounded
4. Less than 230V it is differential compounded
5. Less than 230V it is level compounded
The correct statement’s are?

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 21

An (star connected) Alternator is connected to Delta-star transformer with start neutral earthed. On the star side of transformer a single line to ground fault occurs. This is

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 21

If the winding is delta connected, it does not associated with 0 sequence component current, but only +ve, -ve sequence components exist. Also only +ve & -ve sequence components exist only in line to line fault

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 22

Snubber circuit is used to limit the rate of

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 23

The unit of mobility is:

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 23

Mobility= drift velocity/Electric field

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 24

In the circuit shown in figure, a Silicon transistor with VBE = 0.7 V and βdc = 100 is used. The Q-point is established at

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 24

DC equivalent of the given circuit

Step (1): KVL for B-E loop
0 - IB 220 k - VBE - IE (2. 2k) + 20 V =0
=> IB (220k) + (1 + β) I2.2k = 19.3 V

Step (2): KVL for C-E loop

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 25

A power supply has a full load voltage of 24V. What is its no-load voltage for 5% regulation.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 25

Voltage - Regulation,

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 26

Assume that the op-amp as the circuits shown below is ideal. Find the current passing through the 2kΩ resistor in the circuit.

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 26


But the current entering into the op-amp terminals is zero. So current through 12k is zero.

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 27

The diode in the circuit given below has VON = 0.7 V but is ideal otherwise. The current (in mA) in the 4kΩ resistor is______ mA

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 27

Correct answer is 0.6 Given circuit is

Here, we have

So bridge is balanced, and hence, no current will flow through diode. The equivalent circuit is shown below.

Current through 4kΩ resistor is

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 28

The system of linear equations:
3x + 4y = 6
2x + 3y = 5
has

Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 28

Auguemented matrix,

Since rank of matrix A as well as auguemented matrix is 2, therefore it has unique solution

Gate Practice Test: Electrical Engineering(EE)- 11 - Question 29
Which of the following is a solution to the differential equation
Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 29
(D + 8) x(t) = 0
D = -8,
So
Gate Practice Test: Electrical Engineering(EE)- 11 - Question 30
The value of the integral where C is the circle |z| = 1
Detailed Solution for Gate Practice Test: Electrical Engineering(EE)- 11 - Question 30


Since both the poles lie outside the unit circle therefore according to Cauchey – Integral, the integration is zero
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