To perform product of maxterms Boolean function must be brought into
If (211)x = (152)8 , then the value of base x is
11001, 1001 and 111001 correspond to the 2’s complement representation of the following set of numbers
All are 2’s complement of 7
A signed integer has been stored in a byte using 2’s complement format. We wish to store the same integer in 16-bit word. We should copy the original byte to the less significant byte of the word and fill the more significant byte with
See a example
A computer has the following negative numbers stored in binary form as shown. The wrongly stored number is
The circuit shown in fig. is
From table it is clear that it is a MOD–3 counter.
The counter shown in fig. is
It is a down counter because 0 state of previous FFs change the state of next FF. You may trace the following sequence, let initial state be000
The counter shown in fig. counts from
It is a down counter because the inverted FF output drive the clock inputs. The NAND gate will clear FFs A and B when the count tries to recycle to 111. This will produce as result of 100. Thus the counting sequence will be 100, 011, 010, 001, 000, 100 etc.
The mod-number of the asynchronous counter shown in fig. is
It is a 5 bit ripple counter. At 11000 the output of NAND gate is LOW. This will clear all FF. So it is a Mod 24 counter. Note that when 11000 occur, the CLR input is activated and all FF are immediately cleared. So it is a MOD 24 counter not MOD 25.
The frequency of the pulse at z in the network shown in fig. is
10-bit ring counter is a MOD–10, so it divides the 160 kHz input by 10. therefore, w = 16 kHz. The four-bit parallel counter is a MOD–16. Thus, the frequency at x = 1 kHz. The MOD–25 ripple counter produces a frequency at y = 40 Hz. (1 kHz/25 = 40 Hz).
The four-bit Johnson Counter is a MOD-8. This, the frequency at z = 5 Hz.
The three-stage Johnson counter as shown in fig. is clocked at a constant frequency of fc from the starting state of Q2 Q1Q0 = 101. The frequency of output Q2 Q1Q0 will be
We see that 1 0 1 repeat after every two cycles, hence frequency will be fc/2
The counter shown in the fig. has initially Q2Q1Q0 = 000. The status of Q2 Q1Q0 after the first pulse is
At first cycle
A 4 bit ripple counter and a 4 bit synchronous counter are made by flips flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
In ripple counter delay 4Td = 40 ns.
The synchronous counter are clocked simultaneously, then its worst delay will be equal to 10 ns.
A 4 bit modulo–6 ripple counter uses JK flip-flop. If the propagation delay of each FF is 50 ns, the maximum clock frequency that can be used is equal to
4 bit uses 4 FF
The initial contents of the 4-bit serial-in-parallel-out right-shift, register shown in fig. is 0 1 1 0. After three clock pulses are applied, the contents of the shift register will be
Consider the signed binary number A = 01010110 and B = 1110 1100 where B is the 1’s complement and MSB is the sign bit. In list-I operation is given, and in list-II resultant binary number is given.
The correct match is
The simplified form of a logic function
If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
On multiplying the decimal number continuously by 2, the binary equivalent is obtained.