Test: Architecture Of 8051 - Computer Science Engineering (CSE) MCQ

In some instructions, the Accumulator and B register are used to store the operands.

 B register is used to store one of the operands for multiply and divide instructions. In other instructions, it may just be used as a scratch pad.

The set of flags of program status word contains the status information and is considered as one of the special function registers.

The 8051 stack is not a top-down data structure, like other Intel processors.

The architecture of 8051 consists of 4 latches and driver pairs are alloted to each of the four on-chip I/O ports. It contains two 16-bit timer registers.

 The transmit buffer of serial data buffer is a parallel-in serial-out register.

The serial data register has two buffers. The transmit buffer is a parallel-in serial-out register and receive buffer is a parallel-in serial-out register.

The registers, TMOD and TCON contain control and status information about timers/counters.

The registers, PCON and SCON contain control and status information about serial port.

The oscillator circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator.