Test: Data Path & Control Unit - Computer Science Engineering (CSE) MCQ

The data path is the collection of functional units such as arithmetic logic units or multipliers. The data path is required to perform data processing operations.
Typically, in a microprocessor, the units in at least one of the datapaths would be: instruction registers, decode latch, ALU registers, load-store unit, writeback unit, and the memory.
To perform any operation in the CPU, data follows a specific path within the CPU to execute the instruction. 

Memory capacity = 16K × 16 = 2¹⁴ × 2⁴
Memory Capacity is of the form = 2^m × 2ⁿ
Address lines required = m = 14
Data Lines required = 2ⁿ = 16

Hardwired v/s micro-programmed control unit:- To execute an instruction, the control unit of the CPU must generate the required control signal in the proper sequence. There are two approaches used for generating the control signals in proper sequence as Hardwired Control unit and the Micro-programmed control unit.

Central Processing Unit (CPU) consists of the following features:

• CPU is considered the brain of the computer.
• CPU performs all types of data processing operations.
• It stores data, intermediate results, and instructions (program).
• It controls the operation of all parts of the computer.

Extended Binary Coded Decimal Interchange Code is an eight-bit character encoding used mainly on IBM mainframe and IBM midrange computer operating systems.
EBCDIC was devised in 1963 and 1964 by IBM. It is an eight-bit character encoding, developed separately from the seven-bit ASCII encoding scheme.

A chip having 150 gates will be classified as LSI (large-scale integration).
Large-scale integration (LSI) is the process of integrating or embedding thousands of transistors on a single silicon semiconductor microchip.

Hence the correct answer is LSI.

Control signals are provided by a hardwired circuit in hardwired control techniques. The main goal of the control unit is to produce the control signal in the correct order. The speed of a hardwired control unit can be optimized.
Hence statement I is correct
Indirect addressing mode needs two memory references to fetch operand as the address of the operand is not given in instruction but the address field contains the address where the address of the operand is stored.
Hence statement II is correct.

Concept:
The important assumption that is considered here is that all the three features are considered individually and not in effect of each other.

1. Data bus capability – If the bus size is increased, more words can be fetched and accommodated in a single CPU cycle. This ultimately affects the processing power of the system.
2. Addressing scheme – Optimising the addressing scheme can improve processing power hugely as some addressing schemes consume less processing time as compared to others. Similarly, poor choice of addressing scheme can affect the processing power.
3. Clock speed – As clock speed improves, the processing power goes up. Hence, both are inevitably linked.

The purpose of the Interface unit is to resolve the differences that exist between the central computer and each peripheral. 
The Major Differences are:-

• Peripherals are electromechanical and electromagnetic devices and CPU and memory are electronic devices. Therefore, a conversion of signal values may be needed.
• The data transfer rate of peripherals is usually slower than the transfer rate of the CPU and consequently, a synchronization mechanism may be needed.
• Data codes and formats in the peripherals differ from the word format in the CPU and memory.
• The operating modes of peripherals are different from each other and must be controlled so as not to disturb the operation of other peripherals connected to the CPU.

To Resolve these differences, computer systems include special hardware components between the CPU and Peripherals to supervises and synchronizes all input and out transfers.
Hence the correct answer is Interface unit.

SRAM (static RAM) is random access memory (RAM) that retains data bits in its memory as long as power is being supplied.
Inside a dynamic RAM chip, each memory cell holds one bit of information and is made up of two parts: a transistor and a capacitor.
As DRAM has a capacitor, it continuously leaks current. Therefore it requires frequent refresh which consumes power. Hence, DRAM is slower than SRAM.