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When any interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
When any interrupt is enabled, then it goes to the vector table where the address of the ISR is placed.
What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or the contents of the IE register becomes null.
After RETI instruction is executed then the pointer will move to which location in the program?
When the RETI instruction is executed, it will execute the instruction present at the top of the stack (which is the PC’s value i.e after the interrupt enable instruction).
Which pin of the external hardware is said to exhibit INT0 interrupt?
INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low levelled pulse.
Which bit of the IE register is used to enable TxD/RxD interrupt?
IE.D4 is used to enable RS interrupt or the serial communication interrupt.
Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?
For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled interrupts.
Why normally LJMP instructions are the topmost lines of the ISR?
There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available.
Which register is used to make the pulse a level or a edge triggered pulse?
TCON register is used to make any pulse level or edge triggered one.
What is the disadvantage of a level triggered pulse?
In a level triggered pulse, if the signal does not becomes high before the last instruction of the ISR, then the same interrupt will be caused again, so monitoring of pulse is required for a level triggered pulse.
What is the correct order of priority that is set after a controller gets reset?
EX0 >T0 > EX1> T1>TxD/RxD. This is the correct order of priority that is set after a controller gets reset.