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Test: Interrupt Programming


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10 Questions MCQ Test | Test: Interrupt Programming

Test: Interrupt Programming for Computer Science Engineering (CSE) 2022 is part of Computer Science Engineering (CSE) preparation. The Test: Interrupt Programming questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Interrupt Programming MCQs are made for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Interrupt Programming below.
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Test: Interrupt Programming - Question 1

When any interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?

Detailed Solution for Test: Interrupt Programming - Question 1

When any interrupt is enabled, then it goes to the vector table where the address of the ISR is placed.

Test: Interrupt Programming - Question 2

 What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?

Detailed Solution for Test: Interrupt Programming - Question 2

When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or the contents of the IE register becomes null.

Test: Interrupt Programming - Question 3

After RETI instruction is executed then the pointer will move to which location in the program?

Detailed Solution for Test: Interrupt Programming - Question 3

 When the RETI instruction is executed, it will execute the instruction present at the top of the stack (which is the PC’s value i.e after the interrupt enable instruction).

Test: Interrupt Programming - Question 4

Which pin of the external hardware is said to exhibit INT0 interrupt?

Detailed Solution for Test: Interrupt Programming - Question 4

INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low levelled pulse.

Test: Interrupt Programming - Question 5

Which bit of the IE register is used to enable TxD/RxD interrupt?

Detailed Solution for Test: Interrupt Programming - Question 5

 IE.D4 is used to enable RS interrupt or the serial communication interrupt.

Test: Interrupt Programming - Question 6

Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?

Detailed Solution for Test: Interrupt Programming - Question 6

For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled interrupts.

Test: Interrupt Programming - Question 7

Why normally LJMP instructions are the topmost lines of the ISR?

Detailed Solution for Test: Interrupt Programming - Question 7

There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available.

Test: Interrupt Programming - Question 8

Which register is used to make the pulse a level or a edge triggered pulse?

Detailed Solution for Test: Interrupt Programming - Question 8

TCON register is used to make any pulse level or edge triggered one.

Test: Interrupt Programming - Question 9

What is the disadvantage of a level triggered pulse?

Detailed Solution for Test: Interrupt Programming - Question 9

In a level triggered pulse, if the signal does not becomes high before the last instruction of the ISR, then the same interrupt will be caused again, so monitoring of pulse is required for a level triggered pulse.

Test: Interrupt Programming - Question 10

What is the correct order of priority that is set after a controller gets reset?

Detailed Solution for Test: Interrupt Programming - Question 10

 EX0 >T0 > EX1> T1>TxD/RxD. This is the correct order of priority that is set after a controller gets reset.

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