Test: Interrupt Structure Of 8051 - Computer Science Engineering (CSE) MCQ

The external interrupts namely INT0(active low) and INT1(active low) can be enabled and programmed using the least significant four bits of TCON register and the Interrupt enable and priority registers.

The bits, EX0 and EX1 individually control the external interrupts, INT0(active low) and INT1(active low). If INT0(active low) and INT1(active low) interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.

Using EA bit, all the interrupts can be enabled or disabled. Using the individual respective bit, the respective interrupt can be enabled or disabled.

 Each interrupt level of 8051 can have two levels of priority namely level 0 and level 1. Level 1 is considered as a higher priority level compared to level 0.

SI interrupt is programmed for level 1 priority.

The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.

 All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.

The minimum duration of the active low interrupt pulse should be equal to the duration of one machine cycle for being sensed, else it will be lost.

If two interrupts, occur simultaneously, then the one with higher priority level and early polling sequence will receive service. The other one with lower priority may get lost there, as there is no mechanism for storing the interrupt requests.

For an interrupt to be guaranteedly served it should have duration of two machine cycles.