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# Test: Interrupt Structure Of 8051

## 10 Questions MCQ Test Microprocessors and Microcontrollers - Notes, Videos, MCQs | Test: Interrupt Structure Of 8051

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This mock test of Test: Interrupt Structure Of 8051 for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 10 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Interrupt Structure Of 8051 (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Interrupt Structure Of 8051 quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Interrupt Structure Of 8051 exercise for a better result in the exam. You can find other Test: Interrupt Structure Of 8051 extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

### The external interrupts of 8051 can be enabled by

Solution:

The external interrupts namely INT0(active low) and INT1(active low) can be enabled and programmed using the least significant four bits of TCON register and the Interrupt enable and priority registers.

QUESTION: 2

### The bits that control the external interrupts are

Solution:

The bits, EX0 and EX1 individually control the external interrupts, INT0(active low) and INT1(active low). If INT0(active low) and INT1(active low) interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.

QUESTION: 3

### EA bit is used to

Solution:

Using EA bit, all the interrupts can be enabled or disabled. Using the individual respective bit, the respective interrupt can be enabled or disabled.

QUESTION: 4

The number of priority levels that each interrupt of 8051 have is

Solution:

Each interrupt level of 8051 can have two levels of priority namely level 0 and level 1. Level 1 is considered as a higher priority level compared to level 0.

QUESTION: 5

The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is

Solution:

SI interrupt is programmed for level 1 priority.

QUESTION: 6

The interrupt bit that when set works at level 1, and otherwise at level 0 is

Solution:

The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.

QUESTION: 7

All the interrupts at level 1 are polled in the second clock cycle of the

Solution:

All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.

QUESTION: 8

The minimum duration of the active low interrupt pulse for being sensed without being lost must be

Solution:

The minimum duration of the active low interrupt pulse should be equal to the duration of one machine cycle for being sensed, else it will be lost.

QUESTION: 9

If two interrupts, of higher priority and lower priority occur simultaneously, then the service provided is for

Solution:

If two interrupts, occur simultaneously, then the one with higher priority level and early polling sequence will receive service. The other one with lower priority may get lost there, as there is no mechanism for storing the interrupt requests.

QUESTION: 10

For an interrupt to be guaranteedly served it should have duration of

Solution:

For an interrupt to be guaranteedly served it should have duration of two machine cycles.