Test: Logic Families - 2

Universal Logic Gates:- In addition to the NOT, AND, OR, and XOR gates, three more common gates are available. These are identical to AND, OR, and XOR, except that the gate output has been negated. These gates are called NAND ('Not AND'), NOR ('Not OR'), and XNOR ('eXclusive Not OR').
NAND gate output is defined as  and similarly,
NOR gate output is defined as, 
NAND and NOR gates are also called Universal Logic Gates.
The reason being that all the basic logic gates (NOT, AND, and OR) can be realized using NAND/NOR gates only.

​Fan-out:

• Fan-out is defined as the maximum number of inputs of the same IC family that a gate can drive without falling outside the specified output voltage limits.
• Higher the fan-out, the higher the current supplying capacity of a gate.
• For example, a fan-out of 5 indicates that the gate can drive (supply current to) at the most 5 inputs of the same IC family.
• CMOS has the highest fan out.
• Standard TTL has the lowest fan out.

While choosing a particular digital IC for an application, its specifications or characteristics should be taken into account.
The main specifications for logic families are as follows:
Fan-in: The number of inputs that can be connected to a logic gate is called its ‘Fan-in’.
Fan-out: The number of units that can be connected to the output of a logic gate is called its ‘Fan-out’.
CMOS has the highest fan-out among the given logic families.
A comparison of the given logic families is as shown: 

Concept:

• In a Common Emitter transistor, if input A is at low potential (Logic0) than, there is no voltage drop across Base Emitter junction and hence no current will flow through the Transistor (Cut Off state). therefore output is at high potential (Logic1).
• In a Common Emitter transistor, if input A is at high potential (Logic1) than, there will be a voltage drop across Base Emitter junction and hence current will flow through the Transistor (Saturation state). therefore output is at low potential (Logic0).

Application:

⇒ It can be NOT or NAND (because the output is inversion of input in these two cases)

⇒ NAND Gate (output is inversion of product of both the inputs)

Now,


∴ Output, X = A⋅B

Concept:

Noise Margin
It is the amount of noise that can be allowed without disturbing the normal operation of the logic gates.

NM_low = V_IL – V_OL

NM_high = V_OH - V_IH

Calculation:
Given voltage levels are V_IL = 2 V  V_OL = 5 V, V_OH = 5 V, V_IH = 3.5 V

Emitter-coupled-logic (ECL):

• Emitter-coupled-logic (ECL) is a BJT logic family that is generally considered the fastest logic available.
• ECL achieves its high-speed operation by employing a relatively small voltage swing and preventing the transistors from entering the saturation region. (Reduces the storage delay time).
• ECL transistor uses differential amplifier configuration as shown:

DCTL:

• No external biasing required
• Since no loading resistor present in the circuit cause low power consumption and very high packing density.
• Also known as integrated injection circuit (I2C)
• Current hogging takes place in DCTL
   

ECL:

• Fastest logic circuit available
• Highest power consumption.
• Do not operate in the saturation region
• Also known as current mode logic.
• ECL is used in clock distribution circuits and other high-frequency applications.
   

I²L (integrated injection logic):

• It is having the best figure of merit (1 Pico joule) among logic families.
• It is having BJT of multiple collectors.
• Due to the absence of a resistor, it uses a small chip area and small power consumption.

Concept:

Complementary Metal-oxide-semiconductor (CMOS) uses complementary & symmetrical pair of P-type & n-type MOSFETS.

• The two important characteristics of CMOS devices are high noise immunity and low power dissipation.
• In CMOS, during static operation at a time, only one MOS is ON i.e. either PMOS or NMOS. So there is no direct path from the power supply to the ground. Hence, Power dissipation in CMOS is low in static operation but it has high power dissipation in dynamic operation.

Calculation:

As the given figure is of CMOS with two inputs.

The upper part is PMOS which is switched on when 0 is applied and NMOS is switched on when 1 is applied.

 

1. When S = 0 is applied, the PMOS connected to S (upper one) will be shorted and P at PMOS will appear across the output in complemented form as shown in fig(A).
So Output = P̅

2. Now when S = 1 is applied, the NMOS connected to S (lower one) will be shorted, and due to which ground will appear across the output and the circuit will go in a high impedance state as shown in fig(B).
Hence option (2) is the correct answer.

While choosing a particular digital IC for an application, its specifications or characteristics should be taken into account.
The main specifications for logic families are as follows:
Fan-in: The number of inputs that can be connected to a logic gate is called its ‘Fan-in’.
Fan-out: The number of units that can be connected to the output of a logic gate is called its ‘Fan-out’.

Concept:

1. Feature Size: The minimum feature size is the size or the width at which a transistor or any type of material on the silicon surface can be drawn at.
2. If the minimum feature size can be reduced, this means that the transistor length can be reduced effectively making the transistor smaller with the same electrical properties.
3. This allows for lower current flow between the junction for the same purpose and lesser heat dissipation.

The minimum line width is 2 × minimum feature size  ---(1)

Calculation:
Given:
Minimum feature size = 25 μm
Now the minimum line width can be calculated from equation (1)
Minimum line width = 2 × 25 μm
Minimum line width = 50 μm 
Hence option (3) is the correct answer.

The most important parameters for evaluating and comparing logic families are:

• Power dissipation
• Propagation delay
• Noise margin
• Fan-out (loading)

General comparison of three commonly available logic families is explained in the following table:

Inverter

• This is equal to NOT gate in the digital circuitry.
• The output of this is a compliment of the input.

This can be built from the transistors like BJT, MOSFET, etc…

The CMOS inverter consists of the NMOS and the PMOS field-effect transistors connected in one below the other.

 

When In = Low
PMOS will be shorted and output will be High.
When In = High
NMOS will be shorted and output will be Low.
Hence it acts as an inverter.

Two universal gates are NAND and NOR.

NAND:
In this gate, output of logic gate is false only when both the inputs are true. It is the complement of AND gate.
NOR gate: Output of this logic gate is true when both inputs are false.
Truth Table:

Unipolar Logic Families:

• The device in which the conduction of current is due to either majority carrier or minority carrier is called Unipolar.
• It mainly uses Unipolar devices like MOSFET.
• These logic families have the advantages of high speed and lower power consumption than Bipolar families.

These are classified as:

• PMOS or P-Channel MOS Logic Family
• NMOS or N-Channel MOS Logic Family
• CMOS Logic Family

Fanout

• It is the number of Standard loads (input current of the driven gate), the output of a gate to the same logic family.

Fanout high

Let I_OH = 200 μA and I_IH = 40 μA
G can drive 5 standard loads.

Fanout low

Effective Fanout = min (Fanout_HIGH , Fanout_LOW)

Calculation:
Given I_OL(max) = 32 mA, I_IL(max) = 1.6 mA, I_OH(max) = 400 uA, I_IH(max) = 10 uA