Examine these two statements carefully and select the answers to these items using the code given below:
Statement (I): When all inputs of a NAND gate are shorted to get a single input, single output gate, it becomes an inverter.
Statement (II): When all inputs of a NAND gate are at logic ‘0’ level, the output is at logic ‘0’ level.
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The output of logic circuit given below represents _______ gate.
The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is
What will be the fundamental frequency for the following circuit if each inverter delay is 100 nsec?
How many AND and OR gates are required to realise Y = AB + BC + CD?
32 docs|15 tests
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32 docs|15 tests
|