Test: Multiple BUS Organisation


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10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Multiple BUS Organisation

Test: Multiple BUS Organisation for Computer Science Engineering (CSE) 2022 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Multiple BUS Organisation questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Multiple BUS Organisation MCQs are made for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Multiple BUS Organisation below.
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Test: Multiple BUS Organisation - Question 1

The general purpose registers are combined into a block called as ______

Detailed Solution for Test: Multiple BUS Organisation - Question 1

Answer: c
Explanation: To make the access of the registers easier, we classify them into register files.

Test: Multiple BUS Organisation - Question 2

 In ______ technology, the implementation of the register file is by using an array of memory locations.

Detailed Solution for Test: Multiple BUS Organisation - Question 2

Answer: a
Explanation: By doing so the access of the registers can be made faster.

Test: Multiple BUS Organisation - Question 3

In a three BUS architecture, how many input and output ports are there ?

Detailed Solution for Test: Multiple BUS Organisation - Question 3

Answer: c
Explanation: That is enabling reading from two locations and writting into one.

Test: Multiple BUS Organisation - Question 4

For a 3 BUS architecture, is the below code correct for adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End

Detailed Solution for Test: Multiple BUS Organisation - Question 4

Answer: a
Explanation: We have assumed the names of the three BUSes has A, B and C.

Test: Multiple BUS Organisation - Question 5

The main advantage of multiple bus organisation over single bus is __________

Test: Multiple BUS Organisation - Question 6

 CISC stands for _________

Detailed Solution for Test: Multiple BUS Organisation - Question 6

Answer: c
Explanation: The CISC machines are well adept at handling multiple BUS organisation.

Test: Multiple BUS Organisation - Question 7

 If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).

Detailed Solution for Test: Multiple BUS Organisation - Question 7

Answer: c
Explanation: The value will be much lower in case of multiple BUS organisation.

Test: Multiple BUS Organisation - Question 8

In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.

Detailed Solution for Test: Multiple BUS Organisation - Question 8

Answer: a
Explanation: The MUX can be used to either select the BUS or to increment the PC

Test: Multiple BUS Organisation - Question 9

There exists a seperate block consisting of various units to decode an instruction. 

Detailed Solution for Test: Multiple BUS Organisation - Question 9

Answer: a
Explanation: This block is used to decode the instruction and place it in the IR.

Test: Multiple BUS Organisation - Question 10

There exists a seperate block to increment the PC in multiple BUS organisation.

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