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The general purpose registers are combined into a block called as ______
Explanation: To make the access of the registers easier, we classify them into register files.
In ______ technology, the implementation of the register file is by using an array of memory locations.
Explanation: By doing so the access of the registers can be made faster.
In a three BUS architecture, how many input and output ports are there ?
Explanation: That is enabling reading from two locations and writting into one.
For a 3 BUS architecture, is the below code correct for adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End
Explanation: We have assumed the names of the three BUSes has A, B and C.
The main advantage of multiple bus organisation over single bus is __________
CISC stands for _________
Explanation: The CISC machines are well adept at handling multiple BUS organisation.
If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
Explanation: The value will be much lower in case of multiple BUS organisation.
In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.
Explanation: The MUX can be used to either select the BUS or to increment the PC
There exists a seperate block consisting of various units to decode an instruction.
Explanation: This block is used to decode the instruction and place it in the IR.
There exists a seperate block to increment the PC in multiple BUS organisation.