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Electrical Engineering (EE) Exam  >  Electrical Engineering (EE) Tests  >  Test: NMOS And CMOS Fabrication - Electrical Engineering (EE) MCQ

Test: NMOS And CMOS Fabrication - Electrical Engineering (EE) MCQ


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10 Questions MCQ Test - Test: NMOS And CMOS Fabrication

Test: NMOS And CMOS Fabrication for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: NMOS And CMOS Fabrication questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: NMOS And CMOS Fabrication MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: NMOS And CMOS Fabrication below.
Solutions of Test: NMOS And CMOS Fabrication questions in English are available as part of our course for Electrical Engineering (EE) & Test: NMOS And CMOS Fabrication solutions in Hindi for Electrical Engineering (EE) course. Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: NMOS And CMOS Fabrication | 10 questions in 10 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study for Electrical Engineering (EE) Exam | Download free PDF with solutions
Test: NMOS And CMOS Fabrication - Question 1
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Lithography is:

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Lithography is the process used to develop a pattern to a layer on the chip.

Test: NMOS And CMOS Fabrication - Question 2
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Silicon oxide is patterned on a substrate using:

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Silicon oxide is patterned on a substrate using Photolithography.

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Test: NMOS And CMOS Fabrication - Question 3
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Positive photo resists are used more than negative photo resists because:

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Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists. Therefore, negative photo resists are-used less commonly in the manufacturing of high-density integrated circuits.

Test: NMOS And CMOS Fabrication - Question 4
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The ______ is used to reduce the resistivity of poly silicon:
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The resistivity of poly silicon is reduced by Doping impurities.

Test: NMOS And CMOS Fabrication - Question 5
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The isolated active areas are created by technique known as:
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To create isolated active areas both the techniques can be used. Among them Local Oxidation of Silicon(LOCOS) is most efficient.

Test: NMOS And CMOS Fabrication - Question 6
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The chemical used for shielding the active areas to achieve selective oxide growth is:
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Selective oxide growth is achieved by shielding the active areas. Silicon nitride (Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide growth.

Test: NMOS And CMOS Fabrication - Question 7
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The dopants are introduced in the active areas of silicon by:
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Two ways to add dopants are diffusion and ion implantation.

Test: NMOS And CMOS Fabrication - Question 8
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To grow the polysilicon gate layer, the chemical used for chemical vapour deposition is:
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Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated again to grow the polysilicon layer by chemical vapor deposition.

Test: NMOS And CMOS Fabrication - Question 9
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The process by which Aluminium is grown over the entire wafer , also filling the contact cuts is:
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Aluminum is sputtered over the entire wafer, it also fills the contact cuts

Test: NMOS And CMOS Fabrication - Question 10
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Chemical Mechanical Polisihing is used to:
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The pad oxide and nitride are removed using a Chemical Mechanical Polishing (CMP) step.

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