Electrical Engineering (EE)  >  Test: NMOS & CMOS Fabrication Download as PDF

Test: NMOS & CMOS Fabrication


Test Description

20 Questions MCQ Test | Test: NMOS & CMOS Fabrication

Test: NMOS & CMOS Fabrication for Electrical Engineering (EE) 2023 is part of Electrical Engineering (EE) preparation. The Test: NMOS & CMOS Fabrication questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: NMOS & CMOS Fabrication MCQs are made for Electrical Engineering (EE) 2023 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: NMOS & CMOS Fabrication below.
Solutions of Test: NMOS & CMOS Fabrication questions in English are available as part of our course for Electrical Engineering (EE) & Test: NMOS & CMOS Fabrication solutions in Hindi for Electrical Engineering (EE) course. Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: NMOS & CMOS Fabrication | 20 questions in 20 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study for Electrical Engineering (EE) Exam | Download free PDF with solutions
1 Crore+ students have signed up on EduRev. Have you?
Test: NMOS & CMOS Fabrication - Question 1

 nMOS fabrication process is carried out in

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 1

 nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.

Test: NMOS & CMOS Fabrication - Question 2

_____ impurities are added to the wafer of the crystal

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 2

p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.

Test: NMOS & CMOS Fabrication - Question 3

 What kind of substrate is provided above the barrier to dopants?

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 3

Above a layer of silicon dioxide which acts as barrier, insulating layer is provided upon which other layers may be deposited and patterned.

Test: NMOS & CMOS Fabrication - Question 4

The photoresist layer is exposed to

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 4

The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.

Test: NMOS & CMOS Fabrication - Question 5

In nMOS device, gate material could be

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 5

In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.

Test: NMOS & CMOS Fabrication - Question 6

The commonly used bulk substrate in nMOS fabrication is

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 6

In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.

Test: NMOS & CMOS Fabrication - Question 7

 In nMOS fabrication, etching is done using

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 7

In nMOS fabrication, etching is done using hydroflouric acid or plasma. Etching is a process used to remove layers from the surface.

Test: NMOS & CMOS Fabrication - Question 8

Heavily doped polysilicon is deposited using

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 8

The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.

Test: NMOS & CMOS Fabrication - Question 9

 In diffusion process, ______ impurity is desired

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 9

 Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.

Test: NMOS & CMOS Fabrication - Question 10

Contact cuts are made in

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 10

Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.

Test: NMOS & CMOS Fabrication - Question 11

Interconnection pattern is made on

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 11

The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.

Test: NMOS & CMOS Fabrication - Question 12

 _______ is used to suppress unwanted conduction

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 12

Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.

Test: NMOS & CMOS Fabrication - Question 13

 CMOS technology is used in developing

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 13

CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.

Test: NMOS & CMOS Fabrication - Question 14

 CMOS has

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 14

Some of the properties of CMOS are that it has low power dissipation, high packing density and low noise margin.

Test: NMOS & CMOS Fabrication - Question 15

 In CMOS fabrication, nMOS and pMOS are integrated in same substrate.

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 15

In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate. n-type and p-type devices are formed in the same structure.

Test: NMOS & CMOS Fabrication - Question 16

P-well is created on

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 16

P-well is created on n substrate to accommodate n-type devices whereas p-type devices are formed in the ntype substrate.

Test: NMOS & CMOS Fabrication - Question 17

 Oxidation process is carried out using

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 17

 Oxidation process is carried out using high purity oxygen and hydrogen. Oxidation is a process of oxidizing or being oxidised.

Test: NMOS & CMOS Fabrication - Question 18

 Photoresist layer is formed using

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 18

Light sensitive polymer is used to form the photoresist layer. Photoresist is a light sensitive material used to form patterned coating on a surface.

Test: NMOS & CMOS Fabrication - Question 19

 In CMOS fabrication,the photoresist layer is exposed to

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 19

The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.

Test: NMOS & CMOS Fabrication - Question 20

 Few parts of photoresist layer is removed by using

Detailed Solution for Test: NMOS & CMOS Fabrication - Question 20

Few parts of photoresist layer is removed by treating the wafer with basic or acidic solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater than 7.

Use Code STAYHOME200 and get INR 200 additional OFF
Use Coupon Code
Information about Test: NMOS & CMOS Fabrication Page
In this test you can find the Exam questions for Test: NMOS & CMOS Fabrication solved & explained in the simplest way possible. Besides giving Questions and answers for Test: NMOS & CMOS Fabrication, EduRev gives you an ample number of Online tests for practice