Test: NMOS & CMOS Inverter - Electrical Engineering (EE) MCQ

 Inverters are needed for restoring logic levels for NAND and NOR gates, sequential and memory circuits.

A basic inverter circuit consists of transistor with source connected to ground and a load resistor connected from drain to positive supply rail Vdd.

Depletion mode transistors are preferred to be used as load in inverter circuits as it occupies lesser area and are produced on silicon sibstrate unlike resistors.

 For the depletion mode transistor, gate is connected to source so it is always on and only the characteristic curve Vgs=0 is relevant.

 In nMOS inverter configuration, depletion mode devices are called as pull up and enhancement mode devices are called as pull down transistor.

nMOS inverter can be represented using two transistors, depletion mode pMOS transistor followed by nMOS transistor. Input is given to the nMOS.

The ratio of Zp.u/Zp.d where Z is determined by the length to width ratio of the transistor, is given by 4/1.

Pass transistors are transistor used as switches in series with lines carrying logic levels due to its isolated nature of the gate.

An inverter driven directly from output of another has the ratio of 4/1 and if driven through one or more pass transistors has the ratio of 8/1.

 In nMOS depletion mode pull-up, dissipation is high since current flows Vin = logical 1.

CMOS inverter has five distint regions of operation which can be determined by plotting CMOS inverter current versus Vin.

If n-transistor conducts and has large voltage between source and drain, then it is in saturation.

If p-transistor is conducting and has small voltage between source and drain, then it is said to be in unsaturated resistive region.

 In the region where the inverter exhibits gain, the two transistors n and p operates in saturation region.

When both the transistors are in saturation, then act as current sources so that the equivalent circuit is two current sources between Vdd and Vss.

 If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic levels is symmetrically disposed about the point.

 Mobility is affected by transverse electric field and thus also depends on Vgs and the mobility of p-device and n-device are inherently unequal.

Explanation: In CMOS inverter, transistor is a switch having finite on resistance and infinite off resistance.

CMOS inverter has low output impedance and this makes it less prone to noise and disturbance.

Input resistance of CMOS inverter is extremely high as it is a perfect insulator and draws no dc input source.