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Test: Noise Margin - Electrical Engineering (EE) MCQ


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10 Questions MCQ Test - Test: Noise Margin

Test: Noise Margin for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: Noise Margin questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Noise Margin MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Noise Margin below.
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Test: Noise Margin - Question 1

Noise Margin is :

Detailed Solution for Test: Noise Margin - Question 1

Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by difference between VOH and VIH or VIL and VOL.

Test: Noise Margin - Question 2

The VIL is found from transfer characteristic of inverter by:

Detailed Solution for Test: Noise Margin - Question 2

The VIL is the input voltage at which the slope of the transition will be equal to -1.

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Test: Noise Margin - Question 3

The VIH is found from transfer characteristic of inverter by:

Detailed Solution for Test: Noise Margin - Question 3

The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points we will find the slope to be -1.

Test: Noise Margin - Question 4

The relation between threshold voltage and Noise Margin is:

Detailed Solution for Test: Noise Margin - Question 4

None.

Test: Noise Margin - Question 5

The Lower Noise Margin is given by:

Detailed Solution for Test: Noise Margin - Question 5

 Noise margin = VIL-VOL.

Test: Noise Margin - Question 6

The Higher Noise Margin is given by:

Detailed Solution for Test: Noise Margin - Question 6

Noise margin =VOH – VIH.

Test: Noise Margin - Question 7

The Uncertain or transition region is between:

Detailed Solution for Test: Noise Margin - Question 7

In Input the uncertain region is VIH and VIL.

Test: Noise Margin - Question 8

The noise immunity ____________ with noise margin

Detailed Solution for Test: Noise Margin - Question 8

The noise immunity is directly proportional to noise margin.

Test: Noise Margin - Question 9

If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :

Detailed Solution for Test: Noise Margin - Question 9

 Logic output 0 from first gate is considered as logic input 0 at second gate as it lies within the range.

Test: Noise Margin - Question 10

If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :

Detailed Solution for Test: Noise Margin - Question 10

The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.

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