Test: PIO 8255 (Programmable Input – Output Port) - Computer Science Engineering (CSE) MCQ

The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

Port C can function independently either as input or as output ports.

By programming the bits of control word register, the operations of the ports are specified.

The data bus buffer is controlled by read/write control logic.

RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

 If reset pin is enabled then the control word register is cleared.