Test: S-R Latch

SR Latch:

The truth table for SR latch is:

From the above table, when both the inputs of a latch are high, The out is indeterminate.

(i) Latches are level-triggered (outputs can change as soon as the inputs changes)  
(ii) Flip-Flop is edge-triggered (only changes state when a control signal goes from high to low or low to high).
(iii) Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal.
(iv) Level triggering is a type of triggering that allows a circuit to become active when the clock pulse is on a particular level.

• Switch bounce or contact bounce or even called chatter is a common problem associated with mechanical switches and relays.
• Switch bouncing is not a major problem when we deal with the power circuits, but it causes problems while we are dealing with the logic and digital circuits.
•  Hence, to remove the bouncing from the circuit Switch Debouncing Circuit is used.
• The hardware debouncing technique uses an S-R latch to avoid bounces in the circuit along with the pull-up resistors. 
• S-R circuit is the most effective of all debouncing approaches
• The figure below is a simple debouncing circuit that is often used.

SR Latch:

• In an S-R latch, activation of the S input sets the circuit, while activation of the R input resets the circuit.
• If both S and R inputs are activated simultaneously, the circuit will be in an invalid condition.

Application:

• Latches are used to keep the conditions of the bits to encode binary numbers.
• Latches are single-bit storage elements that are widely used in computing as well as data storage.
• Latches are used in the circuits like power gating & clock as a storage device.

Latches are memory devices and can store one bit of data for as long as the device is powered.

As the name suggests, latches are used to "latch onto" information and hold it in place.

Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.

The reason for using the latch in an output port is simple, we do not want to lose the result of any operation.

So, in order to not lose it, we use a latch, so that it holds the information as long as new information is overwritten onto it.

An 8-bit latch can be used to interface the output of a microprocessor to other devices.

The 74LS373 octal latch and the 74LS374 octal D flip-flop are popular microprocessor interface chips.

Note:

Tristate buffer is commonly used to interface input devices.

From the given diagram,

S = AQ̅, R = QB

Given that, A = 1, B = 0

S = Q̅, R = 0

The truth table of the S-R latch is:

Let Q = 0,

S = Q̅ = 1, R = 0 ⇒ Q_{n + 1} = 1

Let Q = 1,

S = Q̅ = 0, R = 0 ⇒ Q_{n + 1} = 1

In both the cases, Q_{n + 1} Q̅_{n + 1} = 10

Let as assume t_pd 1 < t_pd 2

x changes state first then y changes

1^st output of X (P = 1, y = 0) ⇒ X₁ = 1

Next output of Y (Q = 1, X₁ = 1) ⇒ Y₁ = 0

2^nd output of X (P = 1, y₁ = 0) ⇒ 1

Hence output x = 1 y = 0 (if t_pd1 < t_pd2)

& Output X = 0 Y = 1 (if t_pd2 < t_pd1)

Concept:

• In the TTL logic gate, open-end or floating end are considered as logic-1.
• For the circuit to work as an S & R latch, S & R should act as logic-0 as well as logic- 1 on requirement.

Analysis:

• If we connect set which is equal to 5 volts, then it will be considered as logic-1.
• If we do not connect 5 Volts to set switch i.e. if we make set switch ‘open’ then it will again be considered as a logic -1, because it is a TTL gate.
• So we have to replace 5 V supply with 0 Volts by connecting it to ground. So logic-0 is also possible for switch ‘set’ & ‘reset’.

Hence for the above circuit to work as an SR latch, 5-volt battery should connect to ground.

Hence option -4 is Correct.

The difference between latches and flip flops is shown

An unclocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip flops have inverting gates inside them, hence in order to have both Q and Q complement available, we have atleast one output labelled.

When both gates are identical and this is “metastable”, and the device will be in an undefined state for an indefinite period.

S input of an SR latch is directly connected to the output Q. So when a high is applied Q output goes high and Q’ low.

The full form of SR is set/reset. It is a type of latch having two stable states.

SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:
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When both inputs of SR latches are low, the latch remains in it’s present state. There is no change in output.