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The expression for MOD number for a ripple counter with N flip-flops is
Ripple Counter: For a ripple counter if the number of flip flops is 'n' then total states are 2n and MOD is 2n
A BCD counter counts 10 states from 0 to 9
It is MOD 10 counter
Number of flips required 4
Ring counter: A n bit ring counter counts n states and mod is "n"
Johnson Counter: A n bit Johnson ring counter has 2n states and the mod is 2n
Calculate the maximum clock frequency at which a 4-bit asynchronous counter can work reliably. Assume the propagation delay of each flip-flop to be 40 ns and the width of the strobe pulse to be 20 ns.
Given that, propagation delay of each flip-flop = 40 ns
Width of the strobe pulse = 20 ns
Total propagation delay = 40 × 4 + 20 = 180 ns
Maximum clock frequency
A cascade of three identical modulo-5 counters has an overall modulus of
Concept: Overall modulus of a cascaded system is the product of their individual modules.
For example: A counter of modulus p, modulus q, and modulus r is cascaded, then the modulus of the overall counter is p × q × r
The modulus of all three counters is 5
Then the overall modulus = 5 × 5 × 5 = 125
A 6 bit counter is used to count from 0, 1, 2, ......n. The value of n is _____
Concept: A n bit counter has 2n states and can count from 0 to 2n-1
n = 6
so it will count from 0 to 26 - 1
= 0 to 63
Race-around condition occurs in
Race around condition:
For JK flip-flop if J, K, and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition.
This can be eliminated by using the following methods.
The Master-slave configuration is used in a flipflop to eliminate the race around condition but not to store two bits of information.
An eight-bit binary ripple UP counter with a modulus of 256 is holding the count 01111111. What will be the count after 135 clock pulses?
01111111 → 127
After 135 clock cycles, we will get
127 + 135 = 262
∴ The total number of clock pulses will be 262
As the modulus is 256,
After 256 clock pulses, the sequence will repeat.
262 = 256 + 6
∴ 00 00 00 00
257 → 00 00 00 01
258 → 00 00 00 10
259 → 00 00 00 11
260 → 00 00 01 00
261 → 00 00 01 01
262 → 00 00 01 10
Which of the following is not a sequential circuit?
In a D flip flop, if the present state is 1, what will be the next state of the output at the complement end?
Truth table of D Flip-Flop:
A frequency counter needs to measure a frequency of 30 Hz. If the gating time is 2 seconds then determine how many times the trigger level has been crossed?
digital frequency counters that use a direct counting approach count the number of times the input signal crosses a given trigger voltage (and in a given direction, e.g. moving from negative to positive) in a given time. This time is known as gate time.
The frequency is equal to the number of crossings of the trigger level in one second. Therefore
Gate time = 2 sec
Frequency = 30 Hz
∴ Trigger level crossing = frequency x gate time = 30 x 2 = 60
A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For the sequence (1,0,1) and input data (1,1,0,1,0,0,1,1,0,1,0,1,1,0), what is the output of this detector?
A sequence detector is a sequential circuit that outputs 1 when a particular pattern of bits sequentially arrives at its data input.
Given input data = 1,1,0,1,0,0,1,1,0,1,0,1,1,0
Overlapping sequences detectable.
The below table shows the output for each sequence.
The output = 0,1,0,0,0,0,0,1,0,1,0,0