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Test: Single BUS Organisation 1 & 2


20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Single BUS Organisation 1 & 2


Description
This mock test of Test: Single BUS Organisation 1 & 2 for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 20 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Single BUS Organisation 1 & 2 (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Single BUS Organisation 1 & 2 quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Single BUS Organisation 1 & 2 exercise for a better result in the exam. You can find other Test: Single BUS Organisation 1 & 2 extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

The CPU is also called as ________

Solution:

Answer: b
Explanation: ISP stands for Instruction Set Processor.

QUESTION: 2

A common strategy for performance is making various functional units operate parallely. 

Solution:

Answer: a
Explanation: By parallely accessing data we can have a pipelined processor.

QUESTION: 3

The PC gets incremented

Solution:

Answer: c
Explanation: The PC always points to the next instruction to be executed.

QUESTION: 4

 Which register in the processor is single directional ?
Solution:

Answer: a
Explanation: The MAR is single directional as it just takes the address from the processor bus and passes it to the external bus.

QUESTION: 5

The transparent register/s is/are __________
Solution:

Answer: d
Explanation: These registers are usually used to store temporary values.

QUESTION: 6

Which register is connected to the MUX ?
Solution:

Answer: a
Explanation: The MUX can either read the operand from the Y register or increment the PC.

QUESTION: 7

The registers,ALU and the interconnecting path together are called as ______
Solution:
QUESTION: 8

The input and output of the registers are governed by __________
Solution:
QUESTION: 9

When two or more clock cycles are used to complete data transfer it is called as ________
Solution:

Answer: b
Explanation: This is basically used in systems without edge-triggered flip flops.

QUESTION: 10

________ signal is used to show complete of memory operation.
Solution:

Answer: a
Explanation: MFC stands for Memory Function Complete.

QUESTION: 11

Is the below code segment correct, for the addition of two numbers ?
R1in, Yin
R2out, Select Y, ADD , Zin
Zout, R3in 
Solution:

Answer: a
Explanation: This is the gate transfer notation, which indicates the usage of switches to control the flow of data.

QUESTION: 12

The completion of the memroy operation is indicated using ______ signal.
Solution:

Answer: a
Explanation: MFC stands for Memory Function Complete.

QUESTION: 13

 _________ signal enables the processor to wait for the memory operation to complete.
Solution:

Answer: c
Explanation: This signal stands for Wait For Memory Function Complete.

QUESTION: 14

The small extremly fast, RAM’s all called as ________
Solution:

Answer: b
Explanation: Cache’s are extremly essential in single BUS organisation to achieve fast operation.

QUESTION: 15

The main virtue for using single Bus structure is
Solution:
QUESTION: 16

To extend the connectivity of the processor bus we use ______
Solution:

Answer: a
Explanation: The PCI BUS basically is used to connect ot memory devices.

QUESTION: 17

The bus used to connect the monitor to the CPU is
Solution:

Answer: b
Explanation: The SCSI (Small Component System Interconnect) is used to connect to display devices.

QUESTION: 18

The ISA standard Buses are used to connect ___________
Solution:
QUESTION: 19

 ANSI stands for _____
Solution:

Answer: a
Explanation: It is one of the standards of developing a BUS.

QUESTION: 20

IBM developed a bus standard for their line of computers ‘PC AT’ called
Solution:

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