Test: Single BUS Organisation 1 & 2
20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Single BUS Organisation 1 & 2
| 1 Crore+ students have signed up on EduRev. Have you? |
Answer: b
Explanation: ISP stands for Instruction Set Processor.
A common strategy for performance is making various functional units operate parallely.
Answer: a
Explanation: By parallely accessing data we can have a pipelined processor.
Answer: c
Explanation: The PC always points to the next instruction to be executed.
Which register in the processor is single directional ?
Answer: a
Explanation: The MAR is single directional as it just takes the address from the processor bus and passes it to the external bus.
Answer: d
Explanation: These registers are usually used to store temporary values.
Answer: a
Explanation: The MUX can either read the operand from the Y register or increment the PC.
The registers,ALU and the interconnecting path together are called as ______
The input and output of the registers are governed by __________
When two or more clock cycles are used to complete data transfer it is called as ________
Answer: b
Explanation: This is basically used in systems without edge-triggered flip flops.
________ signal is used to show complete of memory operation.
Answer: a
Explanation: MFC stands for Memory Function Complete.
Is the below code segment correct, for the addition of two numbers ?
R1in, Yin
R2out, Select Y, ADD , Zin
Zout, R3in
Answer: a
Explanation: This is the gate transfer notation, which indicates the usage of switches to control the flow of data.
The completion of the memroy operation is indicated using ______ signal.
Answer: a
Explanation: MFC stands for Memory Function Complete.
_________ signal enables the processor to wait for the memory operation to complete.
Answer: c
Explanation: This signal stands for Wait For Memory Function Complete.
The small extremly fast, RAM’s all called as ________
Answer: b
Explanation: Cache’s are extremly essential in single BUS organisation to achieve fast operation.
The main virtue for using single Bus structure is
To extend the connectivity of the processor bus we use ______
Answer: a
Explanation: The PCI BUS basically is used to connect ot memory devices.
The bus used to connect the monitor to the CPU is
Answer: b
Explanation: The SCSI (Small Component System Interconnect) is used to connect to display devices.
The ISA standard Buses are used to connect ___________
Answer: a
Explanation: It is one of the standards of developing a BUS.
IBM developed a bus standard for their line of computers ‘PC AT’ called
|
18 videos|63 docs|37 tests
|
|
Use Code STAYHOME200 and get INR 200 additional OFF
|
Use Coupon Code |
|
18 videos|63 docs|37 tests
|
Download free EduRev App
Related tests with Test: Single BUS Organisation 1 & 2
|
|
|
|
|
|
© EduRev
|
Follow Us
|