Test: Single BUS Organisation 1 & 2


Test Description

20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Single BUS Organisation 1 & 2

Test: Single BUS Organisation 1 & 2 for Computer Science Engineering (CSE) 2022 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Single BUS Organisation 1 & 2 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Single BUS Organisation 1 & 2 MCQs are made for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Single BUS Organisation 1 & 2 below.
Solutions of Test: Single BUS Organisation 1 & 2 questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: Single BUS Organisation 1 & 2 solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Single BUS Organisation 1 & 2 | 20 questions in 20 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
1 Crore+ students have signed up on EduRev. Have you?
Test: Single BUS Organisation 1 & 2 - Question 1

The CPU is also called as ________

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 1

Answer: b
Explanation: ISP stands for Instruction Set Processor.

Test: Single BUS Organisation 1 & 2 - Question 2

A common strategy for performance is making various functional units operate parallely. 

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 2

Answer: a
Explanation: By parallely accessing data we can have a pipelined processor.

Test: Single BUS Organisation 1 & 2 - Question 3

The PC gets incremented

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 3

Answer: c
Explanation: The PC always points to the next instruction to be executed.

Test: Single BUS Organisation 1 & 2 - Question 4

 Which register in the processor is single directional ?

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 4

Answer: a
Explanation: The MAR is single directional as it just takes the address from the processor bus and passes it to the external bus.

Test: Single BUS Organisation 1 & 2 - Question 5

The transparent register/s is/are __________

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 5

Answer: d
Explanation: These registers are usually used to store temporary values.

Test: Single BUS Organisation 1 & 2 - Question 6

Which register is connected to the MUX ?

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 6

Answer: a
Explanation: The MUX can either read the operand from the Y register or increment the PC.

Test: Single BUS Organisation 1 & 2 - Question 7

The registers,ALU and the interconnecting path together are called as ______

Test: Single BUS Organisation 1 & 2 - Question 8

The input and output of the registers are governed by __________

Test: Single BUS Organisation 1 & 2 - Question 9

When two or more clock cycles are used to complete data transfer it is called as ________

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 9

Answer: b
Explanation: This is basically used in systems without edge-triggered flip flops.

Test: Single BUS Organisation 1 & 2 - Question 10

________ signal is used to show complete of memory operation.

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 10

Answer: a
Explanation: MFC stands for Memory Function Complete.

Test: Single BUS Organisation 1 & 2 - Question 11

Is the below code segment correct, for the addition of two numbers ?
R1in, Yin
R2out, Select Y, ADD , Zin
Zout, R3in 

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 11

Answer: a
Explanation: This is the gate transfer notation, which indicates the usage of switches to control the flow of data.

Test: Single BUS Organisation 1 & 2 - Question 12

The completion of the memroy operation is indicated using ______ signal.

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 12

Answer: a
Explanation: MFC stands for Memory Function Complete.

Test: Single BUS Organisation 1 & 2 - Question 13

 _________ signal enables the processor to wait for the memory operation to complete.

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 13

Answer: c
Explanation: This signal stands for Wait For Memory Function Complete.

Test: Single BUS Organisation 1 & 2 - Question 14

The small extremly fast, RAM’s all called as ________

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 14

Answer: b
Explanation: Cache’s are extremly essential in single BUS organisation to achieve fast operation.

Test: Single BUS Organisation 1 & 2 - Question 15

The main virtue for using single Bus structure is

Test: Single BUS Organisation 1 & 2 - Question 16

To extend the connectivity of the processor bus we use ______

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 16

Answer: a
Explanation: The PCI BUS basically is used to connect ot memory devices.

Test: Single BUS Organisation 1 & 2 - Question 17

The bus used to connect the monitor to the CPU is

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 17

Answer: b
Explanation: The SCSI (Small Component System Interconnect) is used to connect to display devices.

Test: Single BUS Organisation 1 & 2 - Question 18

The ISA standard Buses are used to connect ___________

Test: Single BUS Organisation 1 & 2 - Question 19

 ANSI stands for _____

Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 19

Answer: a
Explanation: It is one of the standards of developing a BUS.

Test: Single BUS Organisation 1 & 2 - Question 20

IBM developed a bus standard for their line of computers ‘PC AT’ called

Use Code STAYHOME200 and get INR 200 additional OFF
Use Coupon Code
Information about Test: Single BUS Organisation 1 & 2 Page
In this test you can find the Exam questions for Test: Single BUS Organisation 1 & 2 solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Single BUS Organisation 1 & 2, EduRev gives you an ample number of Online tests for practice