Test: Storage Elements - Electrical Engineering (EE) MCQ

 Two phase non-overlapping clock signal is easily available and works better and effectively and this clock will be used throughout storage system.

 Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.

Bits or data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.

Some of the comparative assessment factor for storage elements are area requirement, estimated dissipation per bit stored and volatility.

nMOS design with buried contacts needs lesser area than CMOS design and this can be estimated by calculating space stored by each bit in register cell.

In CMOS design, static dissipation is very small since only the switching dissipation will be significant particularly at high speeds.

Each inverter stage has 8:1 ratio and in nMOS register cell, atleast one inverter should always be on and Zp.u. is given as 4Rs and Zp.d. is given as 1/2Rs.

Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.

 With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.

A bit value is stored for some time by Cg of time period T2 while both RD and WR are made low.

Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.

Overhead bits are used for sensing. Some amount of over head bits are used in one transisrot dynamic memory cell.

Reading a cell is a detructive operation and the stored bit must be rewritten everytime it is read.

RAM is a pseudo static cell. It stores data indefinitely and refreshing is not necessary.

 Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using a feedback.

Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when layout is made.

Pseudo static RAM cell is a non volatile cell. It is used for long time storage. Non volatile memory is also called as long term memory.

 In RAM arrays, transistor is of minimum size and thus it is incapable of sinking large charges quickly.

 NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.

 In nMOS, NAND gate implementation is impractical because of the large number of gate requiring three or more inputs.