Test: The Mechanism of Interrupts - Computer Science Engineering (CSE) MCQ

Explanation: In the edge-triggered interrupt, the clock edge is used to generate an interrupt. The transition is from a logical low to high or vice versa.

Explanation: In the level-triggered interrupt, the trigger is completely dependent on the logic level. The processors may require the level to be in a certain clock width so that the shorter pulses which are shorter than the minimum pulse width are ignored.

Explanation: After the recognition of the interrupt, and finds that it is not an error condition with the currently executing interrupt, then the interrupt will not be internally executed until the current execution has completed. This point is known as instruction boundary. At this point, the processor will start to internally process the interrupt.

Explanation: The MC68000 and 80×86 family use stack frame for holding the data whereas RISC processors use special internal registers.

Explanation: The RISC processors uses special internal registers to hold data whereas the 80×86 and MC68000 family uses stack register to hold the data.

Explanation: The MC68000, Intel 80×86 and most of the b-bit controllers are based on the stack-based processors whereas PowerPC, DEC alpha, and ARM are RISC families which have a special internal register for holding the data.

Explanation: Some of the processors use internal hardware stack which helps in reducing the external memory cycle necessary to store the stack frame.

Explanation: The MC68000 has an external stack for holding the data. The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins.

Explanation: The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins. These interrupt pins are IP0, IP1, and IP2.

Explanation: The LS148 7-to-3 priority encoder is used in MC68000. This converts the seven external pins into a three-bit binary code.