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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Embedded Systems (Web)  >  Test: RISC Exceptions - Computer Science Engineering (CSE) MCQ

Test: RISC Exceptions - Computer Science Engineering (CSE) MCQ


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20 Questions MCQ Test Embedded Systems (Web) - Test: RISC Exceptions

Test: RISC Exceptions for Computer Science Engineering (CSE) 2024 is part of Embedded Systems (Web) preparation. The Test: RISC Exceptions questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: RISC Exceptions MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: RISC Exceptions below.
Solutions of Test: RISC Exceptions questions in English are available as part of our Embedded Systems (Web) for Computer Science Engineering (CSE) & Test: RISC Exceptions solutions in Hindi for Embedded Systems (Web) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: RISC Exceptions | 20 questions in 20 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Embedded Systems (Web) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: RISC Exceptions - Question 1
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What does MSR stand for?

Detailed Solution for Test: RISC Exceptions - Question 1

Explanation: The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.

Test: RISC Exceptions - Question 2
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 How many supervisor registers are associated with the exception mode?

Detailed Solution for Test: RISC Exceptions - Question 2

Explanation: When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.

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Test: RISC Exceptions - Question 3
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What happens when an exception is completed?

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Explanation: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed.

Test: RISC Exceptions - Question 4
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How many general types of exceptions are there?
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Explanation: There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.

Test: RISC Exceptions - Question 5
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 In which of the exceptions does the external event causes the exception?
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Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.

Test: RISC Exceptions - Question 6
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Which of the exceptions are usually a catastrophic failure?
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Explanation: An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.

Test: RISC Exceptions - Question 7
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 Which of the exceptions allows the system reset or memory fault?
Detailed Solution for Test: RISC Exceptions - Question 7

Explanation: The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.

Test: RISC Exceptions - Question 8
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Which registers are used to determine the completion status?
Detailed Solution for Test: RISC Exceptions - Question 8

Explanation: The completion status can be determined by the information bits in the DSISR and FPSCR registers.

Test: RISC Exceptions - Question 9
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 Which of the following does not support PowerPC architecture?
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Explanation: The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.

Test: RISC Exceptions - Question 10
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Which exceptions are used in the PowerPC for floating point?
Detailed Solution for Test: RISC Exceptions - Question 10

Explanation: . The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.

Test: RISC Exceptions - Question 11
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Which exception is used in the external interrupts and decrementer-caused exceptions?
Detailed Solution for Test: RISC Exceptions - Question 11

Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.

Test: RISC Exceptions - Question 12
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Which of the following can be done to ensure that all interrupts are recognised?
Detailed Solution for Test: RISC Exceptions - Question 12

Explanation: The exception handler performs some kind of handshaking to ensure that all the interrupts are recognised.

Test: RISC Exceptions - Question 13
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How many types of exceptions are associated with the asynchronous imprecise?
Detailed Solution for Test: RISC Exceptions - Question 13

Explanation: Two types of exceptions are associated with the asynchronous imprecise. These are system reset and machine checks.

Test: RISC Exceptions - Question 14
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 How is the internal registers and memories are reset?
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Explanation: By doing the system reset, all the current processing are stopped and the internal registers and the memories are reset.

Test: RISC Exceptions - Question 15
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 How is the machine check exception is taken in an asynchronous imprecise?
Detailed Solution for Test: RISC Exceptions - Question 15

Explanation: The machine check exception is taken only if the ME bit of the MSR is set. If it is cleared, the processor will enter into a check stop state.

Test: RISC Exceptions - Question 16
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 Which of the following are the exceptions associated with the asynchronous imprecise?
Detailed Solution for Test: RISC Exceptions - Question 16

Explanation: The machine check and the system reset are two types of exceptions which are associated with the asynchronous imprecise.

Test: RISC Exceptions - Question 17
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 Which of the following possesses an additional priority?
Detailed Solution for Test: RISC Exceptions - Question 17

Explanation: The synchronous precise exceptions provide additional priority because it is possible for an instruction to generate more than one exception.

Test: RISC Exceptions - Question 18
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Which of the following has more priority?
Detailed Solution for Test: RISC Exceptions - Question 18

Explanation: The system reset has the first priority then comes the machine reset, next priority moves for the instruction dependent, and the next priority is external interrupt, and last priority level goes for the decrementer interrupt.

Test: RISC Exceptions - Question 19
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Which bit controls the external interrupts and the decrementer exceptions?
Detailed Solution for Test: RISC Exceptions - Question 19

Explanation: The EE bit in the MSR controls the external interrupts and the decrementer exceptions.

Test: RISC Exceptions - Question 20
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Which bit controls the machine check exceptions?
Detailed Solution for Test: RISC Exceptions - Question 20

Explanation: The ME bit in the MSR controls the machine check interrupts.

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