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This mock test of Test: Design Of ALU Subsystem for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam.
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QUESTION: 1

Design gives the detailed

Solution:

Design is largely a matter of topology of communication rather than the detailed logic circuit design.

QUESTION: 2

To minimize the design effort, regularity should be

Solution:

Regularity is a qualitatie parameter and it should be high as possible to minimize the design effort required for any system.

QUESTION: 3

Regularity is the ratio of

Solution:

Regularity is the ratio of total transistors in the chip to total transistors that must be designed in detail.

QUESTION: 4

Good design system has regularity in the range of

Solution:

Good design system must have regularity in the range of 50 to 100 or more and regular structures such as memories achieve very high figures.

QUESTION: 5

In the adder, sum is stored in

Solution:

The sum is stored in parallel at the output of the adder from where it may be fed through the shifter and back to the register array.

QUESTION: 6

The shifter must be connected to

Solution:

The shifter is unclocked but must be connected to 4 shift control lines. Carry out and Carry in signal must also be connected.

QUESTION: 7

What is the sum and carry if the two bit number is 1 1 and the previous carry is 0?

Solution:

If the two bit number is 1 1 and the previous carry is 0 the sum is 0 and carry is 1. This can be obtained by first adding the two numbers 1 and 1. Sum will be 0 and carry is 1. Later add the previous carry 0 to it. Now the sum is finally 0 and final carry will be 1.

QUESTION: 8

Which design is preferred in n-bit adder?

Solution:

In n-bit adder, n adder elements must be cascaded with carry out connecting to carry in. This carry chain will have more pass transistors connected in series which will give slow response. Thus suitable buffer can be used in between.

QUESTION: 9

In adders, the previous carry can also be given by

Solution:

In adders, the previous carry signal can also be given using propogate signal pk which is ex-or of two bits ak and bk and also using generate signal gk which is ‘and’ of ak and bk.

QUESTION: 10

Adder using ____ technology can be used for speed improvement

Solution:

Using BiCMOS technology, speed improvement can be obtained by a factor of two over CMOS technology. This arrangement works will lower input voltage swings to achieve higher speed.

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