Test: Design Processes


10 Questions MCQ Test VLSI System Design | Test: Design Processes


Description
This mock test of Test: Design Processes for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 10 Multiple Choice Questions for Electrical Engineering (EE) Test: Design Processes (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Design Processes quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Design Processes exercise for a better result in the exam. You can find other Test: Design Processes extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

Micropocessor has ____ major architectural blocks

Solution:

MIcropocessor has four major architectural blocks – ALU, control unit, I/O unit and memory.

QUESTION: 2

High level of system integration, _____ interconnections

Solution:

High level of system integration usually greatly reduces interconnections which is a weak spot in any system.

QUESTION: 3

Some important features of system are

Solution:

Lower power dissipation, lower weight, lower volume are some of the important features of system.

QUESTION: 4

 Performance is better if power speed product is

Solution:

 Performance is better if power speed product is high. Performance is analysed using this speed power product.

QUESTION: 5

VLSI design is done in ____ approach

Solution:

VLSI design is done in top-down manner with adequate computer aided tools to do the job. Partitioning, generating or building and verification is done.

QUESTION: 6

 Components operating in high frequency should be

Solution:

Components operating in high frequency should be at physically proximate, since one may pay severe penalties for long, high bandwidth interconnects.

QUESTION: 7

 Approach used for design process are

Solution:

Several approaches used for design process are conventional circuit symbols, logic symbols, stick diagrams, mask layouts, architectural block diagrams and floor plans.

QUESTION: 8

Which approach is used to show the relative disposition of subunits?

Solution:

Floor plan is used to show the planned relative disposition of the subunits on the chip and thus on mask layouts.

QUESTION: 9

When a polysilicon crosses a diffusion _____ will be formed

Solution:

When and where ever the polysilicon crosses the diffusion, transistor will be formed.

QUESTION: 10

Two metal layers can be joined by using

Solution:

The first metal layer can be joined with the second one using via. Via is an electrical connection between layers in a physical electronic circuit.

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