Test: Latch-up In CMOS


10 Questions MCQ Test VLSI System Design | Test: Latch-up In CMOS


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This mock test of Test: Latch-up In CMOS for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 10 Multiple Choice Questions for Electrical Engineering (EE) Test: Latch-up In CMOS (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Latch-up In CMOS quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Latch-up In CMOS exercise for a better result in the exam. You can find other Test: Latch-up In CMOS extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

 In latch-up condition, parasitic component gives rise to __________ conducting path

Solution:

In latch-up condition, parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Carefull control during fabrication is necessary to avoid this problem.

QUESTION: 2

Latch-up can be induced by

Solution:

Latch-up can be induced by glitches on the supply rail or by incident radiation.

QUESTION: 3

How many transistors might bring up latch up effect in p-well structure?

Solution:

Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.

QUESTION: 4

Substrate doping level should be decreased to avoid the latch-up effect.
 

Solution:

An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for latch-up problem.

QUESTION: 5

What can be introduced to reduce the latch-up effect?

Solution:

The introduction of guard rings can reduce the effect of latch-up problem. Guard rings are diffusions which decouple the parasitic bipolar transistors.

QUESTION: 6

Which process produces circuit which are less prone to latch-up effect?

Solution:

BiCMOS process produces circuits which are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.

QUESTION: 7

 One of the factor in reducing the latch-up effect is

Solution:

One of the main factor in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher value of holding current is also required.

QUESTION: 8

The parasitic pnp transistor has the effect of _______ carrier lifetime

Solution:

 The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base region.

QUESTION: 9

The reduction in carrier lifetime brings about

Solution:

The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.

QUESTION: 10

Latch-up is the generation of

Solution:

Latch-up is the generation of low-impedance path in CMOS chips between the power suppply and ground rails.

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