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# Test: MOS Circuits Area Capacitance And Delay Unit

## 15 Questions MCQ Test VLSI System Design | Test: MOS Circuits Area Capacitance And Delay Unit

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This mock test of Test: MOS Circuits Area Capacitance And Delay Unit for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 15 Multiple Choice Questions for Electrical Engineering (EE) Test: MOS Circuits Area Capacitance And Delay Unit (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: MOS Circuits Area Capacitance And Delay Unit quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: MOS Circuits Area Capacitance And Delay Unit exercise for a better result in the exam. You can find other Test: MOS Circuits Area Capacitance And Delay Unit extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

### Which of the following mainly constitutes the output node capacitance:

Solution:

Output node capacitance mainly consists of junction parasitic capacitance.

QUESTION: 2

### The junction parasitic capacitance are produced due to:

Solution:

The junction parasitic capacitance are produced due to drain diffusion capacitance.

QUESTION: 3

### The amount of parasitic capacitance at the output node is determined by:

Solution:

The amount of parasitic capacitance is a linear function of drain diffusion area.

QUESTION: 4

The dominant component of the total output capacitance in submicron technology is:

Solution:

Interconnect capacitance becomes dominant component in submicron technology.

QUESTION: 5

Which of the following is dominant component in input capacitance?

Solution:

For input capacitance, gate oxide capacitance is the main component.

QUESTION: 6

The total load capacitance is calculated as the sum of:

Solution:

Total load capacitance = Drain capacitance + interconnect capacitance +input capacitance.

QUESTION: 7

The interconnect capacitance is formed by:

Solution:

Interconnect line between the gates form interconnect capacitance.

QUESTION: 8

The amount of gate oxide capacitance is determined by:

Solution:

The amount of gate oxide capacitance is determined by the area of the gate.

QUESTION: 9

By what amount is Sidewall doping larger than substrate doping concentration.

Solution:

The sidewall doping is 10 times larger.

QUESTION: 10

Zero bias depletion capacitance per unit length at sidewall junctions is given by, (Cj is the zero bias depletion capacitance per unit are

Solution:

Since the doping concentration is 10 times larger.

QUESTION: 11

The typical value of capacitance in pF x 10¯⁴/µm² for gate to channel in λ based design is:

Solution:

The gate to channel capacitance in λ based design is 4 pF x 10¯⁴/µm².

QUESTION: 12

The active capacitance is also called as:

Solution:

Diffusion capacitance is also called as active capacitance.

QUESTION: 13

The value of diffusion capacitance in pF x 10¯⁴/µm² in 2 µm design is:

Solution:

Diffusion capacitance has a value of 8 pF x 10¯⁴/µm².

QUESTION: 14

The value of standard unit of capacitance is:

Solution:

The value of standard unit of capacitance depends on the design style used.

QUESTION: 15

The standard unit of capacitance is defined as:

Solution:

Standard capacitance is capacitance of gate to channel with standard area.