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# Test: Multiplier Systems

## 10 Questions MCQ Test VLSI System Design | Test: Multiplier Systems

Description
This mock test of Test: Multiplier Systems for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 10 Multiple Choice Questions for Electrical Engineering (EE) Test: Multiplier Systems (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Multiplier Systems quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Multiplier Systems exercise for a better result in the exam. You can find other Test: Multiplier Systems extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

### Multipliers are built using

Solution:

A multiplier is an electronic circuit used to multiply two bianry numbers. It is built using binary adders that is full adders.

QUESTION: 2

### Which method uses reduced number of partial products?

Solution:

Multiplication in multipliers is done by obtaining partial products and then summing it up. Modified booth encoding reduces the number of partial products that must be summed.

QUESTION: 3

### Which method is easier to manipulate accumulator content?

Solution:

It is easier to right shift the contents of accumulator than to left shift. This can be used to eliminate the least significant bits of the product.

QUESTION: 4

Which multiplier is very well suited for twos complement numebers?

Solution:

Baugh-wooley method is used to design multipliers that are regular in structure and is very well suited for twos complement numbers.

QUESTION: 5

What is the delay required to perform a single operation in pipelined structure?

Solution:

The delay of one operation through the pipeline is 3n that is it takes 3n clock cycles to obtain a product after X and Y are input.

QUESTION: 6

Latches choosen are

Solution:

The latches choosen are dynamic shift register as the structure will be continuously clocked.

QUESTION: 7

Which method reduces number of cycles of operation?

Solution:

Modified booth encoding algorithm avoids many idle cells in a cellular multiplier as well as reduces the number of cycles compared with the serial-parallel multiplier.

QUESTION: 8

The completion time for multiplication time in baugh-wooley method is

Solution:

The completion time for multiplication in Braun or Baugh-wooley is proportional to 2n where as completion time in Wallace tree method is proportional to log(base 2)(n).

QUESTION: 9

In which method minimum number of adder cells are used?

Solution:

Dadda multipliers are similar to Wallace trees but it has reduced number of adder cells. This is a technique developed from Wallace tree but with an improvement.

QUESTION: 10

Which method is suitable for larger operands?

Solution:

Wallace tree multipliers should be used for larger operands and where the performance is critical.