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# Test: Storage Elements

## 20 Questions MCQ Test VLSI System Design | Test: Storage Elements

Description
This mock test of Test: Storage Elements for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 20 Multiple Choice Questions for Electrical Engineering (EE) Test: Storage Elements (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Storage Elements quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Storage Elements exercise for a better result in the exam. You can find other Test: Storage Elements extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

### Which clock is preferred in storage devices?

Solution:

Two phase non-overlapping clock signal is easily available and works better and effectively and this clock will be used throughout storage system.

QUESTION: 2

### Clock signal Φ2 is to

Solution:

Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.

QUESTION: 3

Solution:

Bits or data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.

QUESTION: 4

Factor for assessment of storage elements are

Solution:

Some of the comparative assessment factor for storage elements are area requirement, estimated dissipation per bit stored and volatility.

QUESTION: 5

Which occupies lesser area?

Solution:

nMOS design with buried contacts needs lesser area than CMOS design and this can be estimated by calculating space stored by each bit in register cell.

QUESTION: 6

In which design, dissipation is less?

Solution:

In CMOS design, static dissipation is very small since only the switching dissipation will be significant particularly at high speeds.

QUESTION: 7

The impedance of pull down transistor in nMOS can be given as

Solution:

Each inverter stage has 8:1 ratio and in nMOS register cell, atleast one inverter should always be on and Zp.u. is given as 4Rs and Zp.d. is given as 1/2Rs.

QUESTION: 8

Data storage time is

Solution:

Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.

QUESTION: 9

A bit is read at T1 when

Solution:

With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.

QUESTION: 10

A bit can be stored when

Solution:

A bit value is stored for some time by Cg of time period T2 while both RD and WR are made low.

QUESTION: 11

Current flows only when

Solution:

Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.

QUESTION: 12

Overhead bits are used for sensing.

Solution:

Overhead bits are used for sensing. Some amount of over head bits are used in one transisrot dynamic memory cell.

QUESTION: 13

Reading a cell is a _______ operation

Solution:

Reading a cell is a detructive operation and the stored bit must be rewritten everytime it is read.

QUESTION: 14

RAM is a _____ cell

Solution:

RAM is a pseudo static cell. It stores data indefinitely and refreshing is not necessary.

QUESTION: 15

Pseudo static RAM cell is built using

Solution:

Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using a feedback.

QUESTION: 16

Cells must be non stackable in RAM storage cell.

Solution:

Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when layout is made.

QUESTION: 17

Which cell is non volatile?

Solution:

Pseudo static RAM cell is a non volatile cell. It is used for long time storage. Non volatile memory is also called as long term memory.

QUESTION: 18

In RAM arrays, transistor is of

Solution:

In RAM arrays, transistor is of minimum size and thus it is incapable of sinking large charges quickly.

QUESTION: 19

Which implementation is slower?

Solution:

NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.

QUESTION: 20

FOR nMOS which implementation is not suitable?

Solution:

In nMOS, NAND gate implementation is impractical because of the large number of gate requiring three or more inputs.