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# Secondary Memory & DMA - 2

## 8 Questions MCQ Test GATE Computer Science Engineering(CSE) 2022 Mock Test Series | Secondary Memory & DMA - 2

Description
This mock test of Secondary Memory & DMA - 2 for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 8 Multiple Choice Questions for Computer Science Engineering (CSE) Secondary Memory & DMA - 2 (mcq) to study with solutions a complete question bank. The solved questions answers in this Secondary Memory & DMA - 2 quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Secondary Memory & DMA - 2 exercise for a better result in the exam. You can find other Secondary Memory & DMA - 2 extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

### Memory mapped I/O involves

Solution:

Memory-mapped I/O performing I/O between CPU and peripheral devices (I/O) in a computer. In memory mapped I/O uses same address space to address both memory and I/O i.e. some address are reserved for I/O devices and rest used for memory. So it works in same way as b/w CPU and memory.

QUESTION: 2

### Compare the following by considering data transfer rate: 1. I/O processor 2. Data communication processor

Solution:

A data communication processor communicates with each terminal through a single pair of wires. Both data and control information are transferred in a serial fashion with the result that the transfer rate is much slower as compare to input output processor.

QUESTION: 3

### Consider a Disk I/O transfer, in which 1500 bytes are to be transferred, but number of bytes on a track is 1000, and rotation speed of disk is 1500 rps but the average time required to move the disk arm to the required track is 15 ms, then what will be total access time?

Solution:

Given:
Ta→ transfer time T
s → average seek time =15 ms
r → rotation speed in rpms = 1500 rps
b → number of bytes to be transferred = 1500 bytes
N → num ber of bytes on a track = 1000 bytes

QUESTION: 4

The computer can execute 1,000,000 instructions per second: A program running on this computer performs on average a one sector read and one sector write for every 200 instructions that it executes. The disk drive handling the I/O transfers requires 0.00010 seconds each to perform the read and write operations. Assuming no overlap of these operations, the percent of CPU time spent in the wait state is

Solution:

•  The response time of I/O devices are magnitude order slower than that of CPU, hence direct interfacing is impossible.
• It is always better to off load the I/O processing to a secondary processor on the I/O controller board then to depend on the primary CPU for I/O processing.
• The variety of I/O devices in the market, requires that separate I/O controller exist for each device.

QUESTION: 5

In a general purpose computer system the CPU, the main memory and the cache may be interconnected via one or more shared system bus(es). However, input/output devices (eg. Hard disk, network interfaces) may only be connected to the system bus through an I/O controller. The following are four statements regarding the requirement for an I/O controller.
1. The capacities of I/O devices are magnitude order larger than that of main memory and hence direct interfacing is impossible.
2. The response times of I/O devices are magnitude order slower than that of CPU and hence direct interfacing is impossible.
3. It is always better to off load the I/O processing to a secondary processor on the I/O controller board then to depend on the primary CPU for I/O processing.
4. The variety of I/O devices in the market requires that a separate I/O controller exist for each device.

Q. What statement(s) best explain the requirement for an I/O controller?

Solution:
QUESTION: 6

An 8-Bit DMA Device is operating is Cycle Stealing Mode (Single Transfer Mode). Each DMA cycle is of 6 clock states and DMA clock is 2 MHz. Intermediate CPU machine cycle takes 2 μs, determine the DMA Data Transfer Rate

Solution:

DMA Clock is 2 MHz ⇒ Each DMA Clock state is 0.5μs
Each DMA Cycle has 6 Clock States ⇒ Each DMA cycle is of 3 μs
In Cycle Stealing 1 CPU and 1 DMA Cycles run alternately and the CPU Cycle takes 2 μs.
Therefore, every 3 + 2 = 5 μs, 1 byte is transferred by DMA device.
Data Transfer Rate = 1000000/5 x 1 Byte
= 200 Kbytes / Sec

QUESTION: 7

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte- wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

Solution:

QUESTION: 8

Consider a disk drive with the following specifications: 16 surfaces, 512 tracks / surface, 512 sectors / track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is

Solution:

Revolution Per minute = 3000 RPM
or 3000/60 = 50 RPS
In one track rotation it can read = 512 KB
In 50 RPS it can read = 512 x 50

⇒ For 4 bytes it takes 156 ns

Percentage of time that the CPU gets blocked
during DMA operation