Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  GATE Computer Science Engineering(CSE) 2025 Mock Test Series  >  Test: Addressing Modes- 2 - Computer Science Engineering (CSE) MCQ

Test: Addressing Modes- 2 - Computer Science Engineering (CSE) MCQ


Test Description

15 Questions MCQ Test GATE Computer Science Engineering(CSE) 2025 Mock Test Series - Test: Addressing Modes- 2

Test: Addressing Modes- 2 for Computer Science Engineering (CSE) 2024 is part of GATE Computer Science Engineering(CSE) 2025 Mock Test Series preparation. The Test: Addressing Modes- 2 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Addressing Modes- 2 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Addressing Modes- 2 below.
Solutions of Test: Addressing Modes- 2 questions in English are available as part of our GATE Computer Science Engineering(CSE) 2025 Mock Test Series for Computer Science Engineering (CSE) & Test: Addressing Modes- 2 solutions in Hindi for GATE Computer Science Engineering(CSE) 2025 Mock Test Series course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Addressing Modes- 2 | 15 questions in 45 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study GATE Computer Science Engineering(CSE) 2025 Mock Test Series for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Addressing Modes- 2 - Question 1

Consider a high-level language statement while [* i - -] then which addressing mode is suitable for it?

Detailed Solution for Test: Addressing Modes- 2 - Question 1

In given while loop i is a pointer variable so autodecrement addressing mode is suitable.

Test: Addressing Modes- 2 - Question 2

Given below are some statements associated with the registers of a CPU. Identify the false statement.

Detailed Solution for Test: Addressing Modes- 2 - Question 2

Program counter contain the address of next instruction to be fetched but not address of executed instruction.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: Addressing Modes- 2 - Question 3

Addressing mode is ______.

Detailed Solution for Test: Addressing Modes- 2 - Question 3

Addressing modes are either explicitly specified or implied by the instruction.

Test: Addressing Modes- 2 - Question 4

Which of the following is not valid class of interrupts?
1. Program
2. Timer
3. I/O
4. Hardware failure

Detailed Solution for Test: Addressing Modes- 2 - Question 4

1, 2, 3, 4 are valid classes of interrupts:
1. Program: generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero etc.
2. Timer: generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.
3. I/O: generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error condition.
4. Hardware failure: generated by failure such as power failure or memories parity error.

Test: Addressing Modes- 2 - Question 5

System calls are usually invoked by using
1. An indirect jump
2. A software interrupt
3. Polling
4. A privileged instruction

Detailed Solution for Test: Addressing Modes- 2 - Question 5

System call is a request in unit like operating system made via software interrupt by an active process for a service performed by the Kernal.

Test: Addressing Modes- 2 - Question 6

Which of the following affects processing power?

Detailed Solution for Test: Addressing Modes- 2 - Question 6

Processing power depends on clock speed, data bus capacity and addressing scheme.

Test: Addressing Modes- 2 - Question 7

Microinstruction length is determined by _____.
1. The maximum number of simultaneous micro operations that must be specified.
2. The way in which the control information is represented or encoded.
3. The way in which the next microinstruction address is specified.

Detailed Solution for Test: Addressing Modes- 2 - Question 7

Format of micro instruction:

Test: Addressing Modes- 2 - Question 8

The following diagram shows, which addressing mode?

Detailed Solution for Test: Addressing Modes- 2 - Question 8

The diagram shows, extended addressing mode. In this, the effective memory address directly specified and it is used by some of the processor and address specified is 16 bit address.

Test: Addressing Modes- 2 - Question 9

The word length of a CPU is defined as

Detailed Solution for Test: Addressing Modes- 2 - Question 9

The word length of processor is defined as the width of a CPU registers i.e. at a time number of instruction process by the processor.

Test: Addressing Modes- 2 - Question 10

In four-address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)

Detailed Solution for Test: Addressing Modes- 2 - Question 10

Four address instruction format:

Test: Addressing Modes- 2 - Question 11

Match List-I with List-ll and select the correct answer using the codes given below the lists:
List-I  
A. Stack overflow
B. Supervisor call
C. Invalid opcode
D. Tinner

List-ll
1. Software interrupt
2. Internal interrupt
3. External interrupt
4. Machine check interrupt

Detailed Solution for Test: Addressing Modes- 2 - Question 11


Test: Addressing Modes- 2 - Question 12

Consider a CPU has 8 general-purpose registers
R0, R1..., R7 and supports the following operations.
ADD Ra, Rb, Rc Add Ra to Rb and store the result to Rc.
MUL Ra, Rb, Rc Multiply Ra to Rb and store the result to Rc.
An operation normally takes one clock cycles, an operation takes two clock cycles if it produces a result required by the immediately following operations. Consider the expression XY + XYZ + YZ, where variables X, Y and Z are initially located in the registers R0, R1 and R2. If contents these registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of XY + XYZ + YZ?

Detailed Solution for Test: Addressing Modes- 2 - Question 12

Test: Addressing Modes- 2 - Question 13

A CPU has an arithmetic unit that adds bytes and then sets its V, C and Z flag bits as follows. The V-bit is set if arithmetic overflow occurs (in 2’s complement arithmetic). The C-bit is set if a carry-out is generated from the most significant bit during an operation. The Z-bit is set if the result is zero. What are the values of the V, C and Z flag bit after 8-bit byte 1100 1100 and 10001111 are added?

Detailed Solution for Test: Addressing Modes- 2 - Question 13


V-bit is set to 1 due to arithmetic overflow.
C-bit is set to 1 because most significant digits generates a carry.
Z-bit is set to 0 because the result of addition is not zero.

Test: Addressing Modes- 2 - Question 14

Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes-the result back onto the stack

Which of the following statements is/are true?
1. If push and pop instructions each require 5 bytes of storage, and arithmetic operations each require 1 byte of storage then the instruction sequence as a whole requires a total of 40 bytes of storage.
2. At the end of execution, zcontainsthe same value as y.
3. At the end of execution, the stack is empty.

Detailed Solution for Test: Addressing Modes- 2 - Question 14

There are 7 pushes and pops for a cost of 35 bytes plus 3 arithmetic instructions for a total of 38 bytes storage.

Test: Addressing Modes- 2 - Question 15

Consider an accumulator-based CPU supports only single address instruction. The CPU supports the following instructions:

Assume CPU uses the memory referencing and each instruction LOAD, STORE and ADD takes one clock cycle. To compute Z = X + Y CPU takes how many minimum number of clock cycles?

Detailed Solution for Test: Addressing Modes- 2 - Question 15

55 docs|215 tests
Information about Test: Addressing Modes- 2 Page
In this test you can find the Exam questions for Test: Addressing Modes- 2 solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Addressing Modes- 2, EduRev gives you an ample number of Online tests for practice

Top Courses for Computer Science Engineering (CSE)

Download as PDF

Top Courses for Computer Science Engineering (CSE)