If the initial state Q_{A} Q_{B} Q_{C} = 110, after how many clocks it get back same value
What will be the current state after two clock pulses further from the number of pulses obtained from the above question?
The divide by N counter as shown in figure. If initially Q_{0} = 0, Q_{1} = 1, Q_{2} = 0. What is the value of N?
So 5mod counter.
Consider the circuit given below with initial state Q_{0} = 1; Q_{1} = Q_{2} = 0. The state of the circuit is given by the value 4Q_{2} + 2Q_{1} + Q_{0 }
Which one of the following is the. correct state sequence of the circuit?
Therefore, the correct state sequence of the circuit is 1, 2, 5, 3, 7, 6, 4.
The following diagram represents a finite state machine which takes as input a binary number from the least significant bit
Which one of the following is TRUE?
Here, for state Q_{0}
When input is 0 output is 0 and it remains in state Q_{0}.
When input is 1 output is 1 and goes to state Q_{1}.
For state Q_{1}.
When input is 0 output is 1, when input is 1 output is 0.
Here state changes from Q_{0} to Q_{1} when there is a 1 as input, in state Q_{1} every input is complemented.
Hence, the given circuit computes 2’s complement of the input number.
Hence (b) is correct answer.
Consider the following circuit
The flipflops are positive edge triggered DFFs. Each state is designated as a two bit string Q_{0}Q_{1} Let the initial state be 00. The state transition sequence is:
The state transitions sequence is
The functional difference between SR flipflop and JK flipflop is that JK flipflop
SR flip flop gives invalid output when both inputs are 1 while JK flipflop toggle the previous output when both inputs are 1. Hence it accepts both inputs 1.
The number of flipflops required in a modulo N counter is
The number of flipflops required for modulo N counter is [ log_{2}(N)].
Consider the figure given below:
Initially all flipflops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?
So 4 clock pulses are needed.
The logic circuit shown below is a 3bit
If input initially are Q_{A}Q_{B}Q_{C} = 000
So after 1st clock pulse Q_{A}Q_{B}Q_{C} = 100
Since, values is incremented so a binary up counter, synchronous since clock provided to all at same time.
The inputs of the JK flipflop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will
To make flipflop working both preset = apart = 1 Since J = K = 0, so it does not change its state i.e. remains in same state.
Consider the following control circuit which contains a 3bit register and a black box with some combinational logic
The initial state of the circuit is Q_{1} Q_{2} Q_{3} = 000.
The circuit generates the control sequence.
(010) → ( 110) → ( 001) →(001) → . . . → ( 001)
On successive clock cycles. Which of the following sets of equations are implemented by the combinational logic in the black box?
‘n’ flipflop will divide the clock frequency by a factor of
nfiipflop divide the clock frequency by a factor of 2^{n}.
Let a_{n} a_{n1} ... a_{1} a_{0} be the binary representation of an integer b. The integer b is divisible by 3 if
Binary representation of 12 is 110 D
So, (q_{0} + q_{2}){q_{1} + q_{3})
= (0 + 1) ( 0 + 1)
= 1  1
= 0
0 is divisible by 3 so, true.
If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by
N stage shift register will take (n  1) x clock time to show the output of final stage.
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