Test: Microprocessor & Digital Logic Families
15 Questions MCQ Test GATE Electrical Engineering (EE) 2023 Mock Test Series | Test: Microprocessor & Digital Logic Families
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Consider the following program of 8085 assembly language:
If the contents of memory location 4A00H, 4A01H and 4A02H, are respectively A7H, 98H and 47H, then after the execution of program contents of memory location 4A02H will be respectively
GRT : MOV M, B
FNSH : HLT
This program find the larger of the two number stored in location 4A00H and 4A01H and store it in memory location 4A002.
A7H > 98H Thus A7H will be stored at 4A02H.
Consider the following program of 8085 assembly language:
Que: The memory requirement for this program is
Operand R, M or implied : 1–Byte instruction
Operand 8–bit : 2–Byte instruction
Operand 16–bit : 3–Byte instruction
3–Byte instruction are: LXI, LDA, JZ, JC, JMP
P–Byte instruction are : MOV, CMP, HLT
Hence memory = 3 x 6 + 1 x 5 = 23 bytes
The instruction, that does not clear the accumulator of 8085, is
All instruction clear the accumulator
Consider the following loop
XRA A
LXI B, 0007H
LOOP : DCX B
JNZ LOOP
This loop will be executed
The instruction XRA will set the Z flag. LXI and DCX does not alter the flag. Hence this loop will be executed 1 times.
How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM?
The contents of accumulator after the execution of following instruction will be
MVI A, A7H
ORA A
RLC
The contents of bit D7 are placed in bit D0
The contents of accumulator after the execution of following instructions will be
MVI A, B7H
ORA A
RAL
RAL instruction rotate the accumulator left through carry.
The contents of the accumulator after the execution of the following program will be
MVI A, C5H
ORA A
RAL
RRC instruction rotate the accumulator right and D0 is placed in D7 .
Consider the following set of instruction
If BYTE1 = 07H, then content of A, after the execution of program will be
This program multiply BYTE1 by 10. Hence content of A will be 46H.
07H = 0710 , 7 x 10 = 70, 7010 = 46H
Consider the following program
MVI A,BYTE1
RRC
RRC
If BYTE1 = 32H, the contents of A after the execution of program will be
Contents of Accumulator A = 0011 0010
After First RRC = 0001 1001
After second RRC = 1000 1100
If either one or both the inputs are V(0) = 0 V the corresponding FET will be OFF, the voltage across the load FET will be 0 V, hence the output is VDD . If boths inputs are V(1) = VDD, both M1 and M2 are ON and the output is V(0) = 0 V. It satisfy NAND gate.
The circuit shown in fig. acts as a
If both the inputs are at V(0) = 0 V, the transistor M1 and M2 are OFF, hence the output is V(1) = VDD . If either one or both of the inputs are at V(1) = VDD , the corresponding FET will be ON and the output will be V (0) = 0 V. Hence it is a NOR gate.
The circuit shown in fig. implements the function
If all inputs A, B and C are HIGH, then input to invertor is LOW and output Y is HIGH. If all inputs are LOW, then input to inverter is also LOW and output Y is HIGH. In all other case the input to inverter is HIGH and output Y is LOW.
The circuit shown in fig. implements the function
The operation of circuit is given below
Consider the CMOS circuit shown in fig. The output Y is
The operation of this circuit is given below :
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22 docs|274 tests
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22 docs|274 tests
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