Cache And Main Memory (Basic Level)- 1


10 Questions MCQ Test Question Bank for GATE Computer Science Engineering | Cache And Main Memory (Basic Level)- 1


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QUESTION: 1

A 32-bit address bus allows access to a memory of capacity

Solution:

With the help of 32 bits, we can identify 232 addresses.
So the memory capacity

QUESTION: 2

Cache memory enhances

Solution:

Cache memory is very small as compared to SM and MM. It stores the data according to principle of locality. As it is on the top most level in the memory hierarchy if data is found in cache the access time is negligible. Hence it enhances effective access time.

QUESTION: 3

Cache memory

Solution:

Cache memory is faster to access than RAM but slower to access than CPU register.

QUESTION: 4

The read /write line

Solution:

Read/write byte enable line belongs to control bus: Read  

QUESTION: 5

Which of the following lists memory types from highest to lowest access speed?

Solution:

QUESTION: 6

According to temporal locality, processes are likely to reference pages that ____.

Solution:

Temporal locality refers to the reuse of specific data and resource, within relatively small time duration i.e. recently.

QUESTION: 7

In caching system, the memory reference made in any short time interval tend to use only a small fraction of the total memory is called ______ .

Solution:

It is the definition of locality principle.

QUESTION: 8

Consider an (n + k) bit instruction with a k-bit opcode and single n-bit address. Then this instruction allow_______operations and_______ addressable memory cells.

Solution:


Number of operations = 2K
Number of addressable memory cells = 2n

QUESTION: 9

Which of the following statements is false about dynamic RAM?

Solution:

Dynamic RAM has one transistor and capacitor while SRAM has lower density because there are total 6 transistors (occupying more space) therefore density of SRAM is more than density of DRAM.

QUESTION: 10

Which of the following statements is false with regard to fully associative and direct mapped cache organizations?

Solution:

Direct mapped caches cannot produce more misses if program refers to memory words that occupy a single tag value i.e. block are filled based on main mm block % cache block.

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