The most relevant addressing mode to write position-independent codes is:
Match the pairs in the following questions:
(A) Base addressing (p) Reentranecy
(B) Indexed addressing (q) Accumulator
(C) Stack addressing (r) Array
(D) Implied addressing (s) Position independent
1 Crore+ students have signed up on EduRev. Have you? Download the App |
When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
Relative mode of addressing is most relevant to writing
Which of the following addressing modes permits relocation without any change whatsoever in the code?
A certain processor supports only the immediate and the direct addressing modes. Which of the following programminglanguage features cannot be implemented on this processor?
The most appropriate matching for the following pairs
X: Indirect addressing 1: Loops
Y: Immediate addressing 2: Pointers
Z: Auto decrement addressing 3: Constantsis
Which is the most appropriate match for the items in the first column with the items in the second column
X. Indirect Addressing I. Array implementation
Y. Indexed addressing II. Writing relocatable code
Z. Base Register Addressing III. Passing array as parameter
Which of the following addressing modes are suitable for program relocation at run time?
I. Absolute addressing
II. Based addressing
III. Relative addressing
IV. Indirect addressing
Consider a three word machine instruction
ADD A[R0], @B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand(source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words,respectively. The first word of the instruction specifies the opcode, the index register designation and the source anddestination addressing modes. During execution of ADD instruction, the two operands are added and stored in thedestination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is:
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.
(1) A[I] = B[J] (a) Indirect addressing
(2) while (*A++); (b) Indexed addressing
(3) int temp = *x (c) Auto increment
Which of the following statements about relative addressing mode is FALSE?
A. It enables reduced instruction size
B. It allows indexing of array element with same instruction
C. It enables easy relocation of data
D. It enables faster address calculation than absolute addressing
The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is
executed.
MOVI Rs, 1 ; Move immediate
LOAD Rd, 1000 (Rs) ; Load from memory
ADDI Rd, 1000 ; Add immediate
STOREI 0 (Rd), 20 ; Store immediate
Which of the statements below is TRUE after the program is executed ?
Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
Consider a hypothetical processor with an instruction of type, which during execution reads a 32-bit word from memory and stores it in a 32-bit register. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider the C struct defined below:
struct data {
int marks [100];
char grade;
int cnumber;
};
struct data student;
The base address of student is available in register R1. The field student.grade can be accessed efficiently using
For the daisy chain scheme of connecting I/O devices, which of the following statements is true?
A hard disk is connected to a 50 MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes 1000 clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires 500 clock cycles for the processor. The hard disk has a transfer rate of 2000 Kbytes/sec and average block transferred is 4 K
bytes. What fraction of the processor time is consumed by the disk, if the disk is actively transferring 100% of the time?
The correct matching for the following pairs is:
(A) DMA I/O (1) High speed RAM
(B) Cache (2) Disk
(C) Interrupt I/O (3) Printer
(D) Condition Code Register (4) ALU
55 docs|215 tests
|
55 docs|215 tests
|