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Test: Cache & Main Memory- 1 - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test Question Bank for GATE Computer Science Engineering - Test: Cache & Main Memory- 1

Test: Cache & Main Memory- 1 for Computer Science Engineering (CSE) 2024 is part of Question Bank for GATE Computer Science Engineering preparation. The Test: Cache & Main Memory- 1 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Cache & Main Memory- 1 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Cache & Main Memory- 1 below.
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Test: Cache & Main Memory- 1 - Question 1

A 32-bit address bus allows access to a memory of capacity

Detailed Solution for Test: Cache & Main Memory- 1 - Question 1

With the help of 32 bits, we can identify 232 addresses.
So the memory capacity

Test: Cache & Main Memory- 1 - Question 2

Cache memory enhances

Detailed Solution for Test: Cache & Main Memory- 1 - Question 2

Cache memory is very small as compared to SM and MM. It stores the data according to principle of locality. As it is on the top most level in the memory hierarchy if data is found in cache the access time is negligible. Hence it enhances effective access time.

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Test: Cache & Main Memory- 1 - Question 3

Cache memory

Detailed Solution for Test: Cache & Main Memory- 1 - Question 3

Cache memory is faster to access than RAM but slower to access than CPU register.

Test: Cache & Main Memory- 1 - Question 4

The read /write line

Detailed Solution for Test: Cache & Main Memory- 1 - Question 4

Read/write byte enable line belongs to control bus: Read  

Test: Cache & Main Memory- 1 - Question 5

Which of the following lists memory types from highest to lowest access speed?

Detailed Solution for Test: Cache & Main Memory- 1 - Question 5

Test: Cache & Main Memory- 1 - Question 6

According to temporal locality, processes are likely to reference pages that ____.

Detailed Solution for Test: Cache & Main Memory- 1 - Question 6

Temporal locality refers to the reuse of specific data and resource, within relatively small time duration i.e. recently.

Test: Cache & Main Memory- 1 - Question 7

In caching system, the memory reference made in any short time interval tend to use only a small fraction of the total memory is called ______ .

Detailed Solution for Test: Cache & Main Memory- 1 - Question 7

It is the definition of locality principle.

Test: Cache & Main Memory- 1 - Question 8

Consider an (n + k) bit instruction with a k-bit opcode and single n-bit address. Then this instruction allow_______operations and_______ addressable memory cells.

Detailed Solution for Test: Cache & Main Memory- 1 - Question 8


Number of operations = 2K
Number of addressable memory cells = 2n

Test: Cache & Main Memory- 1 - Question 9

Which of the following statements is false about dynamic RAM?

Detailed Solution for Test: Cache & Main Memory- 1 - Question 9

Dynamic RAM has one transistor and capacitor while SRAM has lower density because there are total 6 transistors (occupying more space) therefore density of SRAM is more than density of DRAM.

Test: Cache & Main Memory- 1 - Question 10

Which of the following statements is false with regard to fully associative and direct mapped cache organizations?

Detailed Solution for Test: Cache & Main Memory- 1 - Question 10

Direct mapped caches cannot produce more misses if program refers to memory words that occupy a single tag value i.e. block are filled based on main mm block % cache block.

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