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Consider a 5-stage pipeline having stages as Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX) and Write Back (WB). Here we are given 4 instructions. IF, ID, OF and WB stages take 1 clock cycle each, but the EX-stage takes 1 cycle for ADD and SUB, 2 cycles for MUL and 3 cycles for DIV operation. If the operand forwarding technique is used from EX stage to OF stage and the clock rate of pipeline processor is 5 GHz, then choose the correct statement(s), considering the below table:
Here operand forwarding is used from EX to OF stage.
Instruction I3 is dependent on both I1 and I2, so we will fetch the operand for I3 after execution of instruction I1.
When execution of I2 gets completed, we can execute the instruction I3.
Similarly, I4 is dependent on I3. We can only execute I4 after the execution of I3.
Option (1)- True, from above diagrammatic representation, we can see that I3 gets executed in 10th cycle.
Option (2)- True, 3 RAW (Read After Write) dependencies are there
So, total RAW dependencies are 3.
RAW is also known as True dependency.
Option (3)- True, Last instruction I4 gets executed in 11th cycle.
So, total clock cycles required are 11.
Option (3)- True, Total execution time = Total number of clock cycles × clock cycle time
Clock cycle time = 1/Clock rate
Total execution time = 11 × 0.2 ns
= 2.2 ns
= 2.2 x 10–9 sec
= 2.2 x 103 × 10–12 sec
= 2200 x 10–12 sec
= 2200 picoseconds
In microprocessors, the IC (instruction cycle), FC (fetch cycle) and EC (execution cycle) are related as
A non-pipelined CPU has 12 general purpose registers (R0, R1, R2,….R12). Following operations are supported
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate minimum number of clock cycles required to compute the value of the expression XY + XYZ + YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 and contents of these registers must not be modified.
XY + XYZ + YZ = (X × Y) + (X × Y × Z) + (Y × Z) = (X × Y) + (X × Y + Y) × Z
The instructions are non-pipelined and cycles for each instruction is mentioned. Therefore,
X × Y - takes 2 cycles
X × Y + Y - takes 1 cycles (X × Y already done)
(X × Y + Y) × Z - takes 2 cycles
(X × Y) + (X × Y + Y) × Z - takes 1 cycle
Hence, total cycles = 2 + 1 + 2 + 1 = 6
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____.
Data:
For a non-pipelined processor,
Clock cycles to complete one instruction = 5
Instruction operating frequency = 2.5 GHz
One clock cycle time = 1/ (2.5 GHz) = 0.4 ns
For N number of instructions, clock cycles required = 5N
Time taken to complete 5n clock cycles = 0.4*5n = 2N ns
For a pipelined processor,
Stages of pipeline = 5
Overheads associated = 2 GHz
One clock cycle time = 1/ (2 GHz) = 0.5 ns
For n instructions, clock cycles required
Therefore, time taken by pipelined processor:
0.6N (1) + 0.3N [0.05 (1 + 50) + 0.95 (1)] + 0.1N [0.5 (1 + 2) + 0.5 (1)] cycles
= 1.85N cycles
= 1.85N/2 ns
= 0.925N ns
A non-pipeline system takes 50ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
Data:
Time for non-pipelined execution per task = tn = 50 ns
Time for pipelined execution per task = tp = 10 ns
Number of stages in the pipeline = k = 6
Number of tasks = 500
Formula
S = speed up factor
Calculation:
Time for non-pipelined = Tn = tn x Number of tasks
Time for non-pipelined = Tn = 50 x 500
Time for pipelined = Tp = 1st task x k x tp + (All Remaining Tasks (k - 1)) x tp
Time for pipelined = Tp = 1 x 6 x 10 + (500 - 1) x 10
Machine Cycle: Time taken to execute one OPERATION is known as a machine cycle. One instruction will contain 1 to 5 machine cycles.
T-State: The portion of a machine cycle executed in one internal clock pulse is known as T-state.
Steps in the instruction cycle:
Correct sequence: fetch → decode → read effective address → execute
In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.
The main advantages of using pipeline are :
Therefore option 2 is the false statement about Pipelining
Consider the following table:
Which of the following is true about the average CPI of the above given table?
In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.
The main advantages of using pipeline are :
Consider the following sequence of micro-operations.
Which one of the following is a possible operation performed by this sequence?
This sequence of instructions matches with Interrupt Service Routine (ISR) since the sequence of instructions saved the address of current instructions into memory.
Then started executing new address by loading new instruction value to Program counter.
Hence, the correct answer is “option 4”.