Test: Instruction Pipeline - Electronics and Communication Engineering (ECE)

Here operand forwarding is used from EX to OF stage.

Instruction I3 is dependent on both I1 and I2, so we will fetch the operand for I3 after execution of instruction I1.
When execution of I2 gets completed, we can execute the instruction I3.
Similarly, I4 is dependent on I3. We can only execute I4 after the execution of I3.
Option (1)- True, from above diagrammatic representation, we can see that I3 gets executed in 10th cycle.
Option (2)- True, 3 RAW (Read After Write) dependencies are there

So, total RAW dependencies are 3.
RAW is also known as True dependency.
Option (3)- True, Last instruction I4 gets executed in 11th cycle.
So, total clock cycles required are 11.
Option (3)- True, Total execution time = Total number of clock cycles × clock cycle time
Clock cycle time = 1/Clock rate 

Total execution time = 11 × 0.2 ns
= 2.2 ns
= 2.2 x 10^–9 sec
= 2.2 x 10³ × 10^–12 sec
= 2200 x 10–12 sec
= 2200 picoseconds

• The Steps required by the CPU to fetch and execute an Instruction is called an instruction cycle. It consists of fetch and executes cycle.
• Instruction cycle (IC) = Fetch cycle (FC) + Execution cycle (EC)
• The time required by the microprocessor to complete the operation of accessing memory or I/O devices is called a machine cycle.
• Clock time is a known time state. It is reciprocal of clock frequency.
• Instruction cycle > Machine cycle > Clock cycle (time state)

XY + XYZ + YZ = (X × Y) + (X × Y × Z) + (Y × Z) = (X × Y) + (X × Y + Y) × Z
The instructions are non-pipelined and cycles for each instruction is mentioned. Therefore,
X × Y - takes 2 cycles
X × Y + Y - takes 1 cycles (X × Y already done)
(X × Y + Y) × Z - takes 2 cycles
(X × Y) + (X × Y + Y) × Z - takes 1 cycle
Hence, total cycles = 2 + 1 + 2 + 1 = 6

Data:

For a non-pipelined processor,
Clock cycles to complete one instruction = 5
Instruction operating frequency = 2.5 GHz
One clock cycle time = 1/ (2.5 GHz) = 0.4 ns
For N number of instructions, clock cycles required = 5N
Time taken to complete 5n clock cycles = 0.4*5n = 2N ns
For a pipelined processor,
Stages of pipeline = 5
Overheads associated = 2 GHz
One clock cycle time = 1/ (2 GHz) = 0.5 ns
For n instructions, clock cycles required

Therefore, time taken by pipelined processor:
0.6N (1) + 0.3N [0.05 (1 + 50) + 0.95 (1)] + 0.1N [0.5 (1 + 2) + 0.5 (1)] cycles
= 1.85N cycles
= 1.85N/2 ns
= 0.925N ns

Data:
Time for non-pipelined execution per task = tn = 50 ns
Time for pipelined execution per task =  tp = 10 ns
Number of stages in the pipeline = k = 6
Number of tasks = 500
Formula

S = speed up factor

Calculation:
Time for non-pipelined = Tn = tn x Number of tasks
Time for non-pipelined = Tn =  50 x 500
Time for pipelined = Tp​ = 1st task x k x tp + (All Remaining Tasks (k - 1)) x tp
Time for pipelined = Tp​ =  1 x 6 x 10 + (500 - 1) x 10

Machine Cycle: Time taken to execute one OPERATION is known as a machine cycle.  One instruction will contain 1 to 5 machine cycles.
T-State: The portion of a machine cycle executed in one internal clock pulse is known as T-state.

Steps in the instruction cycle:

• First of all, the opcode is fetched by the microprocessor from a stored memory location.
• Then it is decoded by the microprocessor to find out which operation it needs to perform.
• If an instruction contains data or operand address which is still in the memory, the CPU has to perform read operation to get the desired data.
• After receiving the data, it performs to execute the operation.

Correct sequence: fetch → decode → read effective address → execute

In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.
The main advantages of using pipeline are :

• It increases the overall instruction throughput. 
• Pipeline is divided into stages and stages are connected to form a pipe-like structure.
• We can execute multiple instructions simultaneously.
• It makes the system reliable. 
• It increases the program speed.
• It reduces the overall execution time but does not reduce the individual instruction time.

​Therefore option 2 is the false statement about Pipelining

• ALU takes ~30.30% of the total cycles.
• Load takes ~30.30% of the total cycles.
• Store takes ~27.27% of total cycles.
• Branch takes ~12.12% of total cycles.

In pipelining, each step operates parallel with other steps. It stores and executes instructions in an orderly manner.
The main advantages of using pipeline are :

• It increases the overall instruction throughput. 
• Pipeline is divided into stages and stages are connected to form a pipe-like structure.
• We can execute multiple instructions simultaneously.
• It makes the system reliable. 
• It increases the program speed.
• It reduces the overall execution time but does not reduce the individual instruction time.

1. Program counter holds the next instruction value to be executed.
   Here, MBR <- PC means the value of the program counter will get stored in MBR.
2. MAR <- X means some address value X is storing in MAR so to access memory location X.
3. PC <- Y means storing new instruction value Y to the program counter to access new instruction.
4. Memory <- MBR means MBR register will store its value to Memory. This saves the previous value of PC to memory.

This sequence of instructions matches with Interrupt Service Routine (ISR) since the sequence of instructions saved the address of current instructions into memory.
Then started executing new address by loading new instruction value to Program counter.
Hence, the correct answer is “option 4”.