Test: Binary Adders - Electronics and Communication Engineering (ECE) MCQ

Concept:

Carry Lookahead adder: 

A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic.

A carry-look ahead adder improves speed by reducing the amount of time required to determine to carry bits.

It calculates one or more carries before the sum, which reduces the wait time/Ripple delay to calculate the result of the larger value bits of the adder.

The 4-bit carry look-ahead carry adder is shown in the figure given below.

Binary full adder circuit is as shown:

To add two one-bit numbers, along with carrying bit, only two gates are required to propagate carry from input to output.

Therefore, for an n-bit binary adder, 2n number of gates through which a carry has to propagate from input to output.

Total time of addition of a serial adder depends only on the number which has more number of bits. Here in this addition one no. contains 7 bits and another one 5 bits. So 7 clock periods are required to add the two numbers.

Total time = 

C₁₄ will be available after 12 x 15 = 180 n sec.

The FA₁₅ adder will take 12 nsec to generate the carry C₁₅ and 15 nsec to generate the sum S₁₅ after 180 nsec.

So, the worst-case delay is (180 n sec + 15 n sec) = 195 nsec

The carry generation timings are as follows:

T(C₁) = 18 nsec

T(C₂) = (18 + 27) nsec = 45 nsec

T(C₃) = (23 + 45) nsec = 68 nsec

T(C₄) = (32 + 68) nsec = 100 nsec

T(C₅) = (18 + 100) nsec = 118 nsec

T(C₆) = (23 + 118) nsec = 141 nsec

T(C₇) = (27+141) nsec = 168 nsec

C_out = (32 + 168) nsec = 200 nsec

To find the maximum no of addition we have to find the time taken for each addition

Now, sum generation times are as follows:

T(S₈) = (168 + 23) nsec = 191 nsec

T(S₇) = (141 + 169) nsec = 310 nsec

T(S₆) = (118 + 72) nsec = 190 nsec

We see that S₇ appears at t = 310 nsec while the last carry C_out appears before at t = 200 nsec. 

As, S₇ takes the longest time to generate the output. 

Thus, the maximum number of addition per second 

= 

Concept:

The implementation of circuit is shown

To generate S₁ [C₀, A₁, B₁ are required]

To generate C₁ [C₀, A₁, B₁ are required]

To generate S₂ [C₁, A₂, B₂ are required]

To generate C₂ [C₁, A₂, B₂ are required]

Calculation:

Different output and time after which they are generated are:

AND gates = n(n + 1)/2

OR gates = n

So AND gates = 10

OR gates = 4

So 2x + 2y = 28

3 bits full adder contains 2³ = 8 combinational inputs.

The number of different levels of logic gates is represented in a fashion which is known as a logical network.

The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.