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BDL MT Electronics Mock Test - 3 - Electronics and Communication Engineering (ECE) MCQ


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30 Questions MCQ Test BDL MT Electronics Mock Test Series 2025 - BDL MT Electronics Mock Test - 3

BDL MT Electronics Mock Test - 3 for Electronics and Communication Engineering (ECE) 2025 is part of BDL MT Electronics Mock Test Series 2025 preparation. The BDL MT Electronics Mock Test - 3 questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The BDL MT Electronics Mock Test - 3 MCQs are made for Electronics and Communication Engineering (ECE) 2025 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for BDL MT Electronics Mock Test - 3 below.
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BDL MT Electronics Mock Test - 3 - Question 1

Two networks A and B are connected as shown in the below figure. If the Z - parameter matrix of both A and B are given as:

then the Z parameter of the combined network is:

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 1

Concept:

When two networks A and B are connected is the series connection, the Z parameter of the combined network is the sum of the individual network Z-parameters.

Analysis:

Z = ZA + ZB

Important Points

For series-parallel connection, h parameters get added
For series connection, Z parameters get added
For parallel connection, Y parameters get added
For cascading connection ABCD parameters get multiplied

BDL MT Electronics Mock Test - 3 - Question 2

A source of 10 V with an internal resistance of 5 Ω is to be connected through a converter to a load of 20 Ω. For maximum power transfer, what should be the turns ratio of the converter?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 2

Concept:
For maximum power transfer, the load impedance of a transformer reflected on the primary side must equal the input impedance.
The load impedance reflected on the primary side is given by:

ZL = Load impedance at the secondary

Where,
1 : n = turns ratio
Ns = secondary turns
Np = primary turns

Calculation:
Given ZL = 20 Ω
Zin = 5 Ω
The given circuit is drawn as:

For maximum transfer ZL(reflected) must equal Zin, i.e.

n2 = 20/5 = 4
n = 2

Turns ratio is, therefore:
1 : n = 1: 2

BDL MT Electronics Mock Test - 3 - Question 3

The switch S in the circuit has been opened since a very long time. The value of current through resistor R2 immediately after switch is closed, will be

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 3

In the given problem, the circuit has been opened for a very long time, it means that before closing the switch the circuit achieves its steady state.
At time t = 0- (Switch ‘S’ open), the circuit is redrawn as

The current flow in the inductor when switch ‘S’ is open iL(0-).
Applying KVL in the closed-loop,

At time t = 0+ (when switch ‘S’ is closed), the circuit is redrawn as-

The inductor is replaced with a current source.
The current flow in resistor R2 is and its value can be calculated with the help of the current division rule.

BDL MT Electronics Mock Test - 3 - Question 4
A photo diode operating to detect optical signals at wave length 650 nm has internal quantum efficiency of 50%. If the optical power level is 20 μW. What is the photo current generated?
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 4

For a photodiode

Internal quantum efficiency

Responsivity

Efficiency and Responsivity are related as:

= 0.26 A/W

Responsivity is also defined as the ratio of output photo current and incident optical power

0.26 × 20 × 10-6 = Ip

Ip = 5.2 μA
BDL MT Electronics Mock Test - 3 - Question 5

The value of transconductance at a bias voltage of 0 V for the JFET which is having IDSS= 9 mA and Vp = -3V is

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 5

The transconductance of JFET:

Transconductance (gm) is the ratio of change in drain current (δID) to change in the gate to source voltage (δVGS) at a constant drain to source voltage (VDS = Constant).

gm = (δID) / (δVGS) at constant VDS

This value is maximum at VGS = 0 and it is denoted by gmo

The transconductance at any other value of gate to source voltage (gm) can be determined as follows. The expression of drain current (ID) is

Where

IDSS is shorted gated drain current

VGS(off) is Cut Off Gate Voltage

By partial differentiating the expression of drain current (ID) in respect of gate to source voltage (VGS)

At VGS = 0, the transconductance gets its maximum value and that is

In the given question bias voltage is zero hence trance conductance is maximum

Calculation:

Given,

IDSS = 9 mA and Vp = - 3 V

VGS(off) is the modules of Vp

Hence VGS(off) = 3 V

gmo = (2 × 9 × 10-3) / 3

= 6 × 10-3 S = 6 mS

Therefore, The value of transconductance at a bias voltage of 0 V for the JFET is 6 mS

BDL MT Electronics Mock Test - 3 - Question 6

The pole zero plot and the Nyquist plot of the open loop transfer function of a unity feedback system are shown below. Then

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 6

Concept:
Nyquist stability criterion:
N = P – Z
N is the number of encirclements of (-1+j0) point by the Nyquist contour in an anticlockwise direction.
P is the open-loop RHP poles
Z is the closed-loop RHP poles

Analysis:
From the pole-zero plot, we have, P = 1
Where P = Number of open-loop poles in Right Half s – plane
Since P ≠ 0 ⇒ Open-loop system is unstable
consider the Nyquist plot,

∴ Number of encirclements N = P – Z = -2
∴ 1 – Z = -2 ⇒ Z = 3
∴ there are 3 closed-loop poles present in Right Half of s-plane
∴ Hence the closed-loop system is unstable.

BDL MT Electronics Mock Test - 3 - Question 7

A signal x(t) having a frequency component up to 20 kHz is sampled at a rate of 38 kHz and reconstructed through an LPF with unity gain and a cutoff frequency of 25 kHz. Which of the following statement is true?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 7

Let the frequency spectrum of x(t) be as shown:

Given sampling frequency = 38 kHz
The shifted spectrum will be as shown:

We observe that there is aliasing or overlapping happening for f > 18 kHz.
Therefore, we can reconstruct the part of x(f) for f < 18 kHz only.

BDL MT Electronics Mock Test - 3 - Question 8
Let 3 + j4 be a zero of a fourth-order linear phase FIR filter. The complex number which is not a zero of this filter is:
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 8

Concept:

If Z1 is the zero of linear phase filter, then is also zero of the filter.

Analysis:

Given zero Z1 = 3 + j4

Since the given zero is complex, it must occur in conjugate pair, i.e.

Z2 = Z1*

Z2 = 3 - j4

Now:

and

BDL MT Electronics Mock Test - 3 - Question 9

How many comparators would a 12-bit flash ADC require?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 9

No of comparators required for n bit flash type ADC is (2n - 1)
Given that, n = 12
No of comparators = 4095

BDL MT Electronics Mock Test - 3 - Question 10
A 5 bit ladder has a digital input of 11010. Assuming that 0 corresponds to 0 V and 1 corresponds to +10 V, its output voltage will be:
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 10

Concept:

For a ladder-type D/A Converter:

Output Voltage (V0) = Resolution × Decimal Equivalent of binary input.

Where Resolution is given by:

Application:

Given n = 5 and the Digital input = 11010

∵ The Resolution will be:

Since the decimal Equivalent of 11010 = 26

So, V0 = 26 × 0.3125

V0 = 8.125 V

Note: If the full-scale voltage is given, then:

Resolution

BDL MT Electronics Mock Test - 3 - Question 11

The given below logic circuit will work as

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 11


By analysing the above truth table it is giving the expression for 1 bit comparator.

BDL MT Electronics Mock Test - 3 - Question 12

Arrange the procedure of PMOS fabrication in ascending order

  1. Grow the oxide layer
  2. Perform ion implantation
  3. Perform photo lithography and etching to remove SiO2 on source and drain.
  4. Metallization i.e aluminium deposition.
  5. Perform Gate oxidation steps
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 12

Concept:
Ion implantation:

  • It is one of the methods for selective doping, their doping profile is more precisely controlled.
  • Since it is performed at low temperatures, it is suitable for compound semiconductors.
  • With these techniques, we can store the doping profile with greater flexibility.
  • With the diffusion technique, we get peak doping concentration at the surface only but with ion implantation, it is possible to get peak doping concentration below the surface also. Because of this advantage, now a days ion-implantation is mostly preferred in MOS and BJT.
  • With the photolithography process, we can remove the unwanted masking area and allow diffusion on Ion implantation metallization.
  • It is a process to interconnect all the electronic devices present on the wafer so that ohmic contact can form.

Analysis:
Steps to fabricate PMOS in ascending order.

  1. The oxide layer is the starting point for PMOS fabrication.
  2. The Gate oxidation steps are performed to create the Gate oxide layer.
  3. Use photolithography and etching to remove SiO2 on the source and drain.
  4. The ion implantation process is used to create the P-type regions for the PMOS transistors.
  5. Metallization i.e. aluminium deposition.
BDL MT Electronics Mock Test - 3 - Question 13
A good transimpedance amplifier has
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 13

Transresistance or trans-impedance amplifier is normally used as a current to voltage converter which requires low input and low output impedances for its proper operation.

Requirements of input and output impedances for different amplifiers are listed below:

BDL MT Electronics Mock Test - 3 - Question 14

Which of the following is true for an NMOS transistor operating in a linear region?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 14

Three regions of MOSFET operation (nMOS) are:

Linear/ Ohmic/ Triode region:

VGS > Vth

VDS < VGS – Vth

The current equation for a MOSFET in the linear region is given by:

Cut off region:

VGS < Vth

ID = 0

VGS = Gate to source voltage

Vth = Threshold voltage

Saturation region:

VGS > Vth

VDS > VGS – Vth

The current equation for a MOSFET in the saturation region is given by:

BDL MT Electronics Mock Test - 3 - Question 15

The voltage gain of an amplifier without feedback and with negative feedback is 140 and 30 respectively. The percentage of negative feedback (beta) is close to:

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 15

Concept:

The relation between open-loop gain and closed-loop gain is given by:

ACL = AoL/1 + A_oLβ

AOL = Open-loop gain, i.e. gain without feedback

ACL = Closed-loop gain, i.e. gain with feedback

β = feedback factor, i,e, amount of feedback

Calculation:

With AOL = 140, and ACL = 30, we can write:

30 = 140/1 + 140 x β

30 + 30×140×β = 140

4200 β = 110

β = 110/4200

%β = 110/4200 x 100 = 2.61%

% β ≈ 3 %

BDL MT Electronics Mock Test - 3 - Question 16

On a transmission line with standing waves, the distance between two adjacent maxima points of any wave is:

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 16

The voltage and current expressions in a transmission line are given by:​

l = distance from the load

β = Phase Constant = 2π/λ

ΓL = Reflection coefficient at the load.

Let the reflection coefficient at the load end be written in the amplitude and phase form as:

The voltage and current equations will now become:

Variation of Current and Voltage:

  • Whenever ϕ - 2βl = 0 or even multiple of π, the quantity in the brackets will be maximum of (1 + |ΓL|) in the voltage expression and minimum of (1 - |ΓL|) in the current expression.
  • Whenever the voltage is maximum, the current amplitude is minimum.
  • Similarly wherever ϕ - 2βl = odd multiple of π, the voltage is minimum and the current is maximum.
  • From the above observations, the distance between the two adjacent voltage maxima (or minima) or two adjacent current maxima (or minima) is calculated by:

2βl = π

l = λ/2

Note:

The distance between adjacent voltage and current maxima or minima is calculated as:

l = λ/4

BDL MT Electronics Mock Test - 3 - Question 17
Main advantage of fiber optic cable over co-axial cable is
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 17

Optical communication utilizes the principle of total internal reflection by which light signals can be transmitted from one place to another with a negligible loss of energy

Fiber optic cable has many advantages over co-axial cable like high bandwidth, low loss, more security, etc.

The advantages of optical fibers are:

  • Optical fibers have greater information-carrying capacity due to large bandwidth
  • Optical fibers are free from electromagnetic interference and offer high signal security
  • Optical fibers suffer less attenuation than coaxial cable and twisted wire cables.

Of the given option the main advantage is low loss data can be sent through fiber cable across several miles without needing repeaters while co-axial cables need repeaters after a short distance.
BDL MT Electronics Mock Test - 3 - Question 18

The autocorrelation of a wide-sense stationary random process is given by: e-2|τ| .The peak value of the spectral density is

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 18

Concept:
The power spectral density is basically the Fourier transform of the autocorrelation function of the power signal, i.e.
Sx(f) = F.T. { Rx(τ) }
Analysis:
Given, the autocorrelation function of the random signal X(t) as:
Rx(τ) = e-2|τ|
So, its power spectral density is obtained as:
Sx(f) = F.T. { Rx(τ) }


= (1/2(1 - jπf)) + (1/2(1 + jπf)
= 1/1 + π² f²)
The peak value of PSD is at f = 0,
SX(0) = 1

BDL MT Electronics Mock Test - 3 - Question 19

The integral equals to

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 19

Explanation:
We have the integration given as,

Placing the limits we get,

I = 1/5 + 1/21 = 26/105
Hence the required value of integration will be 26/105 .

BDL MT Electronics Mock Test - 3 - Question 20
The improper integral converges to
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 20
Concept:

Improper integral

Converges: If the limit exists when applied and it is a finite number

Diverges: If a limit does not exist or

Calculation:

Given:

Given improper integral

Applying limit by the value a tends to ∞

The improper integral converges to 0.5

BDL MT Electronics Mock Test - 3 - Question 21

The line integral of function , in the counter clock wise direction, along the circle x2 + y2 = 1 at z = 1  is

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 21

Concept:

Green's theorem:

Calculation:

From Green’s Theorem

= - Area of circle (x2 + y2 = 1)
= - π × (1)2
= - π

NOTE -
Stoke's theorem:

Gauss Divergence theorem:

BDL MT Electronics Mock Test - 3 - Question 22
Find the rate of interest when a sum of Rs. 2,600 amounts to Rs. 3,146 in 3 years.
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 22

Given:

Principal = Rs. 2,600

Amount = Rs. 3,146

Time = 3 years

Formula used:

SI = (PRT)/100

A = P + SI

where,

SI is Simple interest, P is Principal, R is Rate, T is Time and A is Amount

Calculations:

According to the question, we have

Simple interest is

⇒ SI = Rs. 3146 - Rs. 2600

⇒ SI = Rs. 546

Now, Rate of interest is

⇒ SI = (PRT)/100

⇒ 546 = (2600 × R × 3)/100

⇒ R = 546/78

⇒ R = 7%

∴ The Rate of interest per annum is 7%.

BDL MT Electronics Mock Test - 3 - Question 23

A batsman in his 12th innings makes a score of 63 runs and thereby increasing his average score by 2, what is his average after the 12th innings?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 23

Given
A batsman in his 12th inning makes a score of 63 runs and thereby increasing his average score by 2
Concept used
Average = Sum of the observation/Total observation
Calculation
Let the total number of runs in 11 innings be "x".
the average number of runs in 11 innings is x/11
Let the total number of runs in 12 innings after scoring 63 runs in 12th innings be x + 63.
Average number of runs in 12th innings is = (x + 63)/12
⇒ (x + 63)/12 = x/11 + 2
⇒ (x + 63)/12 = (x + 22)/11
⇒ 11(x + 63) = 12(x + 22)
⇒ 11x + 693 = 12x + 264
⇒ 693 - 264 = 12x - 11x
⇒ 429 = x
Average of his score after 12 innings
⇒ (x + 63)/12
⇒ (429 + 63)/12
⇒ 41
∴ His average after the 12th innings is 41.

Alternate MethodA batsman in his 12th inning makes a score of 63 runs
His average increases by 2 runs
Increased runs = 11 × 2
Increased runs = 22 runs
His average after 12 innings
⇒ 63 - 22
⇒ 41

BDL MT Electronics Mock Test - 3 - Question 24

If downstream speed of a motorboat is 16 km/h and its upstream speed is 11 km/h. Find the speed of stream in km/h ?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 24

Given:

The downstream speed of a motorboat is 16 km/h

The upstream speed of the motorboat is 11 km/h

Formula:

Speed of current = (Rate of downstream - Rate of upstream)/2

Calculation:

According to the formula,

Speed of current = (16 - 11)/2

⇒ (16 - 11)/2

⇒ 5/2 = 2.5 km/h

The speed of the stream is 2.5 km/h.

BDL MT Electronics Mock Test - 3 - Question 25
Ram, Shyam and Hari can do a piece of work in 30, 45 and 60 days respectively. If they do the work together and earn Rs. 7,800, then what amount Ram will receive?
Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 25

Given:

Ram completed his work in 30 days.

Shyam completed the work in 45 days.

Hari completed the work in 60 days.

Together earing = Rs. 7800

Concept Used:

Wages are directly proportional to the efficiency of workers (one day work)

Calculation:

Let the total number of work be 180 units

One day work of Ram = 6 units

One day work of Shyam = 4 units

One day work of Hari = 3 units

The ratio of their work = 6 : 4 : 3

⇒ The ratio of their earning = 6 : 4 : 3

According to the question, total earning is Rs. 7800

⇒ 3x + 4x + 6x = 7800

⇒ 13x = 7800

⇒ x = 600

Earning of Ram = 6x

⇒ 3600

∴ Amount receive by Ram is Rs. 3600

BDL MT Electronics Mock Test - 3 - Question 26

Find the total surface area of a sphere whose volume is (500/3)π cm3.

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 26

Given:
Volume of the sphere = (500/3)π cm3.
Formula Used:
Volume of Sphere = (4/3)πr3
Total Surface area of Sphere = 4πr2
where,
r = Radius of sphere
Calculation:

According to the question,
Volume of Sphere = (500/3)π
⇒ (4/3)πR3 = (500/3)π
⇒ 4R3 = 500
⇒ R3 = (500/4)
⇒ R = ∛125
⇒ R = 5 cm
So, Total surface area of the sphere = 4πR2
⇒ 4 × π × 52
⇒ 100π cm2
∴ The total surface area of the sphere is 100π cm2.

BDL MT Electronics Mock Test - 3 - Question 27

Select the correct passive form of the given sentence.
The pilot misunderstood the instructions from the control room.

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 27

The correct answer is The instructions from the control room were misunderstood by the pilot.Explanation

  • The given sentence is in an active voice form, hence we need to convert it into a passive voice form.
  • Find the subject (The pilot) and object (The instructions from the control room) of the sentence and exchange their places.
  • The given sentence is in the simple past tense. The passive verb form for simple past is:
    • was/were + past participle form of the verb.
    • So, 'misunderstood' changes to 'were misunderstood' as the main subject is 'instructions'.
  • At last line up the remaining part.

Following these steps, we finally get, The instructions from the control room were misunderstood by the pilot.Other Related Points​​​

  • Certain verbs are followed by certain prepositions. Some of them are given below:
    • vexed at, surprise/astonished/amazed at, known to, tired of, engulfed in, etc.
  • Example:
    • His weird behaviour surprised me. (active)
    • I was surprised at his weird behavior. (passive)
BDL MT Electronics Mock Test - 3 - Question 28

In the following question, out of the four alternatives, select the alternative which best expresses the meaning of the Idiom/ Phrase.

Blow one's own trumpet

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 28

Here the correct answer is To praise oneself.
Explanation

  • Let's look at the meaning of the given idiom:-
  • Blow one's own trumpet - talk boastfully about one's achievements. 
    • For Example - He refused to blow his own trumpet and blushingly declined to speak.
  • Thus, the correct answer is Option 1.

Therefore, the correct meaning of the given idiom is To praise oneself.

BDL MT Electronics Mock Test - 3 - Question 29

Which of the following is not true about the water made available through dams?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 29

The correct answer is 'The water so generated is mainly used in washing.'Explanation

  • Let's refer to the following lines of the passage:
    • There has however been hardly any attempt at questioning the extent of damage caused or in evaluating whether the promises of food, water and prosperity for all have actually been realised.
    • The cost of the project is so stupendous that any water made available will cost so much that governments will have to be forever subsidizing farmers.
    • What long-term impact this massive borrowing will have on the economy is difficult to foresee.
  • Option 1, is incorrect because the passage doesn't mention the use of water will be limited to washing only.
  • Option 2, is correct due to the cost of water made available through dams is high and the government will have to be forever subsidizing farmers.
  • Option 3, is correct because the passage mentions the promises of food, water and prosperity, which means the water will be mainly used in Agriculture.
  • Option 4, is correct because the cost of construction of Dam is high as mentioned in the passage.
  • Thus, from above, the correct answer is option 1.
BDL MT Electronics Mock Test - 3 - Question 30

L is the father of P. R is the sister of P. S is the only son of R. L and V have only one daughter. How is P related to S?

Detailed Solution for BDL MT Electronics Mock Test - 3 - Question 30

The family chart is as follows:

i) L is the father of P.
ii) R is the sister of P.
iii) S is the only son of R.
iv) L and V have only one daughter.
Drawing the family tree as per the given information:

Thus we can see P is related to S as an Uncle.
Hence, the correct answer is "Uncle".

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