Test: Digital Electronics Circuits- 1


25 Questions MCQ Test Basic Electronics Engineering for SSC JE (Technical) | Test: Digital Electronics Circuits- 1


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Attempt Test: Digital Electronics Circuits- 1 | 25 questions in 100 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study Basic Electronics Engineering for SSC JE (Technical) for Electrical Engineering (EE) Exam | Download free PDF with solutions
QUESTION: 1

The voltage levels of a negative logic system

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QUESTION: 2

The output Y of the given circuit is

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QUESTION: 3

The Boolean theorem AB + AC+ BC= AB + AC corresponds to

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QUESTION: 4

Match List- (Circuits) with List-II (Types of integration level) and select the correct answer using the codes given below the lists:

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QUESTION: 5

Y = f(A,B) = IIM (0, 1, 2, 3) represents (M is Maxterm)

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QUESTION: 6

Consider the following statements regarding ICs:

1. ECL has the least propagation delay

.2. TTL has the largest fanout.

3. CMOS has the biggest noise margin.

4. TTL has the lowest power consumption.

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QUESTION: 7

For a logic family

VOH is the minimum output high level voltage

VOH is the maximum output low level voltage

VIH is the minimum acceptable input high level voltage

VIL is the maximm acceptable input low level voltage

The correct relationship among these is

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QUESTION: 8

The logic circuit realied by the circuit shown int the given figure will be

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*Multiple options can be correct
QUESTION: 9

In a negative edge triggered J-K flip-flop, in order to have the output Q state 0, 0 and1 in the next three successive clock pulses, the J-K input states required would be respectively

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QUESTION: 10

The initial state of MOD- 16 down counter is 0110. After 37 clock pulses, the state of the counter will be

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QUESTION: 11

The minimum decimal equivalent of the number 11C.0 is

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QUESTION: 12

(FE35)16 XOR(CB15)16 is equal to

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QUESTION: 13

Which one of the following figures represents the  coincidence logic?

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QUESTION: 14

The figure of merit of a logic family is given by

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QUESTION: 15

Which one of the following statements correctly defines th full-adder? An adder circuit

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QUESTION: 16

The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions

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Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state

QUESTION: 17

Which one of the following can be used as parallel to series converter?

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QUESTION: 18

Consider the following statements:

A multiplexer

1. Selects on e of the several inputs and transmits it to a single output

2. routes the data from a single input to one of many output

3. converts parallel data into serial data

4. is a combinational circuit

Which of these statements are correct?

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QUESTION: 19

Consider the following statements:

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QUESTION: 20

A ring counter consisting of five flip-flops will have

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QUESTION: 21

A crystal oscillator is frequently used in digital circuits for timing purposes because of its

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QUESTION: 22

Which one of the following statement is correct?

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QUESTION: 23

F's complement of (2BFD)hex is

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QUESTION: 24

The number of digit 1 present in the binary representation of 3 × 512 + 7 × 64 + 5 × 8 + 3

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QUESTION: 25

If the output of a logic gate is '1' when all its inputs are at logic '0', the gate is either

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