Test: Electronics - 2 - Physics MCQ

For "n’ bit number of comparators = 2ⁿ - 1
So for ‘5 ' bits =  2⁵ - 1 = 31

Here, output X = 
For XNOR operation when both input same then output will be high.
So, X = 
X = 
So for desired output X = 1 input A, B, C must be high.

When V_i > 0 then op-amp will give negative output, because it is applied at inverting terminal.
So diode (D_i) is F.B. and diode D₂ is R.B. because V'₀ will be negative.
When D₂ OFF so V₀ = 0
Note : There is no need to check V_i < 0 

As Ideal op-amp lias infinite input resistance so there will be no current pass through op-amp V_A and V_B will be virtual ground V_B = V_A = 2 V .

So, 
So, I = 10 mA

LED diodes works in forward bias.
The current flowing though LED is

It is a simple clamper circuit in which the diode is downward direction. So the total signal will be clamp below the reference voltage (2V).
Alternate Method :
When positive terminal of input voltage Vi = +10 V , diode is F.B.
Therefore, V_o = 2V
Apply KVL at the loop.
V_i - V_C - v_o = 0
10 - V_C -2 = 0
V_C = 8V

When negative tenninal of input voltage Vi = -10 V . Diode is reverse biased. Apply KVL at the given loop.
Vi - V_C - V_o = 0
-10-8 = V_o
∴ V_o= -18V

 

For the positive half cycle of V_i , D₁ is forward biased and zener diode is in break down stage.
So, V_o= 0.7 + 6.8 = 7.5 V
For the negative half cycle of V_i,D₂ is forward biased.
So V₀ = -0.7 V.

Firstly check the zener diode is conducting or not conducting. To check this O.C. the Z.D. and calculate open circuit voltage (V_OC )
 By voltage divider rule.
Here, V_OC < V_Z , so Z.D. is not conducting.
Then, V_o = V_OC = 5 V

When V_GS is applied gate is given with negative voltage and therefore positive charges are created in the semi-conductor channel and due to the recombination less no of negative charges or electrons will reaching the drain. Therefore, drain current (l_d) decreases.

Apply KVL for emitter-collector loop
V_CC = I_CR_C + V_CE
when I_C = 0, V_CE = V_CC ⇒ V_CC = 20 V
I_C R_C = V_CC - V_CE when V_CE = 0



 

(i) FET is voltage control current source as

(ii) Op-Any. is voltage control voltage source
Output voltage o f op-amp V₀ at inverting terminal
V₀ ∝ f (Vi)
(iii) BJT current control current source as
I_C = β I_b ⇒ I_C = f  (I_b)

The given circuit can be convert in to Tkevenin’s equivalent circuit.


Applying KVL at base-emitter loop.

Here the base emitter junction is forward bias so there is no chance in cut-off mode of given transistor.
Assume transistor in active mode.
Apply KVL at base-emitter loop.

If V_CE < 0 .2 V, then transistor in saturation.
To check the mode by putting the value R_C in the given option.

So transistor in saturation at RC = 3 kΩ

MUX output

Since, ideal op-amp lias infinite input resistance so there will be no current pass through the op-amp.
So, V_A = V_B and Vc = V_D due to virtual ground concept.
V_A = V_B = 0


= -6 -4
=-10 V

Voltage at inverting terminal V_B = 5 V. Ideal op-amp has infinite input resistance so there will be no current pass through the op-amp. So V_A and V_B will be virtual grounded, V_A = V_B =5V.

Since, V_C = VA = 5 V

Here given p is very large, so I_C  I_E = 1 mA
V' = 1.4 x 10³ x 1 x 10^-3  = 1.4 V
Therefore, output voltage V = V' + V_BE =1.4 + 0.6 = 2V
There is no need to check positive or negative feedback because 2V is available only in option (d).

As the ideal op-amp has infinite input resistance so there will be no current pass through op-amp. In the given circuit the input voltage is applied at inverting terminal so it is work as inverting amplifier.
So output for first op-amp 
Similarly, output for second op-amp

Case-I : When input is positive D₁ is ON and D₂ is OFF. Tlien equivalent circuit is

Case-II : When input is negative D₁ if OFF and D₂ is ON.

(By applying voltage divider rule).

Thus the average value of V_ab = 5 V.

Since, emitter junction is F.B. So BJT is not in cut-offmode. It maybe either active or saturation region.
Let us assume transistor in active region.
Then, applying KVL at base-emitter loop.
2.7 - 40 K I_B -0.7 = 0
40 K I_B = 2
I_B = 0.05 mA

Applying KVL at emitter collector loop.


Since, V_CE < 0.5, so transistor is not in active region it is saturation region.