Electronics and Communication Engineering (ECE) Exam  >  Electronics and Communication Engineering (ECE) Tests  >  GATE ECE (Electronics) Mock Test Series 2025  >  GATE Mock Test Electronics Engineering (ECE)- 3 - Electronics and Communication Engineering (ECE) MCQ

GATE Mock Test Electronics Engineering (ECE)- 3 - Electronics and Communication Engineering (ECE) MCQ


Test Description

65 Questions MCQ Test GATE ECE (Electronics) Mock Test Series 2025 - GATE Mock Test Electronics Engineering (ECE)- 3

GATE Mock Test Electronics Engineering (ECE)- 3 for Electronics and Communication Engineering (ECE) 2024 is part of GATE ECE (Electronics) Mock Test Series 2025 preparation. The GATE Mock Test Electronics Engineering (ECE)- 3 questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The GATE Mock Test Electronics Engineering (ECE)- 3 MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for GATE Mock Test Electronics Engineering (ECE)- 3 below.
Solutions of GATE Mock Test Electronics Engineering (ECE)- 3 questions in English are available as part of our GATE ECE (Electronics) Mock Test Series 2025 for Electronics and Communication Engineering (ECE) & GATE Mock Test Electronics Engineering (ECE)- 3 solutions in Hindi for GATE ECE (Electronics) Mock Test Series 2025 course. Download more important topics, notes, lectures and mock test series for Electronics and Communication Engineering (ECE) Exam by signing up for free. Attempt GATE Mock Test Electronics Engineering (ECE)- 3 | 65 questions in 180 minutes | Mock test for Electronics and Communication Engineering (ECE) preparation | Free important questions MCQ to study GATE ECE (Electronics) Mock Test Series 2025 for Electronics and Communication Engineering (ECE) Exam | Download free PDF with solutions
1 Crore+ students have signed up on EduRev. Have you? Download the App
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 1

A vendor sells his articles at a certain profit percentage. If he sells his articles at 1/4th of his actual selling price then he incurs a loss of 60%. What is his actual profit percentage?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 1
Let the cost price = 100 Rs.

From the options:

If profit % = 60%

Then SP = 160 Rs.

New SP = 160/4 = 40 Rs.

Then,

Percentage loss= (100-40)/100 = 60%

Hence Verified

ALTERNATE:-

Let the selling price is 100

New selling price 100/4 = 25

He suffers a loss of 60%.

CP × 0.4 = 25

CP = 25/0.4 = 62.5

Actual Profit = 100 - 62.5 = 37.5

profit% = 37.5/62.5 × 100 = 60%

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 2

Directions: In the following question, a set of three figures X, Y and Z shows a sequence in which a piece of paper is folded and finally cut from one or more sections. Below these figures, a set of answer figures marked (a), (b), (c) and (d) shows the design which the paper actually acquires when it is unfolded. You have to select the answer figure which most closely resembles the unfolded piece of paper.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 2
After the paper is unfolded, the following pattern will be observed

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 3

Criteria for selecting candidate for internship programme

The candidate:

  1. can preferably start the internship between 18th Oct'17 and 17th Nov'17

  2. are preferably available for duration of 6 months

  3. have computer skills and interest in designing

  4. have already graduated or are currently in any year of study

  5. knows how to deal with customers Nick is a high school student and wants to do an internship as his summer project. He is a very vibrant boy and goes well with people.

Is he the right candidate for the internship?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 3
He is looking for summer internships and November is not summer time.
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 4

In a certain code, BRAIN is written as *%#× and TIER is written as $#+%. How is RENT written in that code?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 4

The code for RENT is %+×$.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 5

Which of the following is MOST OPPOSITE in meaning to Locus?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 5
Locus (noun) -a particular position or place where something occurs or is situated
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 6

Directions: The table lists the size of building lots in the Orange Grove subdivision and the people who are planning to build on those lots. For each lot, installation of utilities costs $12,516. The city charges impact fees of $3,879 per lot. There are also development fees of 16.15 cents per square foot of land.

How much land does Mr. Taylor own in the Orange Grove subdivision?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 6
Look at the chart to see all of the land he owns

The total amount of land he owns is, 8023 + 9004 + 8269 + 6774 = 32070 square feet.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 7

The Union Sports Ministry has approved five lakh rupees from the National Welfare Fund for Sportspersons for Kaur Singh who is suffering from heart disease. Kaur Singh is associated with which of the following sports?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 7
Kaur Singh, former heavyweight Boxer is struggling with the treatment for heart disease and admitted at private hospital in Mohali. Under such circumstances, the Union Sports Ministry has approved five lakh rupees from the National Welfare Fund for Sportspersons for Kaur Singh.
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 8

Two positions of a dice are given. Which of the following numbers would be at the top when 2 is at the bottom?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 8
Number 3 appears in the same position both times.

The pattern of numbers is as given below.

From first orientation, write the numbers in clockwise direction.

3 - 5 - 2

From second orientation, write the numbers in clockwise direction.

3 - 1 - 6

Hence, 2 is opposite to number 6 and 5 is opposite to number 1.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 9

Direction: In given question below there are three statements followed by two conclusions numbered I and II. You have to take the given statements to be true even if they seem to be at variance with commonly known facts. Read all the conclusions and then decide which of the given conclusion logically follows from the given statements disregarding commonly known facts.

Statements:

All oils are sands

Some clays are oils

All clays are rocks

Conclusions:

  1. Atleast some clays are sands
  2. Some oil is not rock
Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 9

Statements

All oils are sands

Some clays are oils

All clays are rocks

Combining all three statements, we get

Conclusions

  1. At least some clays are sandsü
  2. Some oil is not rockû

 

Conclusion 1

Some clays are oils + All oils are sands = Some clays are sands

Hence, Thus, conclusion I follows.

Conclusion 2

Some clays are oils→ conversion → some oils are clays + All clays are rocks = Some oils are rock. Hence, conclusion 2 does not follows.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 10

Walking at th of his usual speed, a man reaches his destination two minutes early. What is the time taken by him to cover the same distance at his usual speed?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 10
The ratio of speeds before and after is 10 : 11. The ratio of time will be 11 : 10.

or,

He takes 1 unit less time now which is given as 2 minutes. The time taken will be 22 minutes at his usual speed.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 11

Given a network with values of components depicted in the figure.

Find the sum of current through 5Ω and 4Ω resistor.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 11
Assume the current in the first loop be I1 and in the second loop be I2.

Then, we can apply mesh analysis to solve it.

Mesh 1: 15I1-10I2 = 5

Mesh 2: -10I1+ 20I2 =10

On solving them, we have

I1 = 1A

I2 = 1A

Thus, sum = 2A

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 12

Which of the following is correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 12

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 13

Given the following system

T{X[n]} = X[n] + 3u[n+1]

Where u[x] represents unit step functions-

Which of the following is a correct representation of the system?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 13
We have,

T{X2[n] + X1[n]} = X1[n] + X2[n] +3u[n+1]

And

T{X1[n]} = X1[n] + 3u[n+1]

T{X2[n]} = X2[n] + 3u[n+1]

Since,

T{X2[n] + X1[n]} ≠ T{X1[n]} + T{X2[n]}

Thus, system is non linear.

T{X[n-no]} = X[n-no] + u[n+1]

≠ y[n-no]

Thus, system is Time Variant.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 14

The width of the depletion layer is proportional to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 14
A depletion region consists of immobile charge carriers such as positive ions and negative ions. The mobile charge carriers such as free electrons are absent in depletion region. The p-side of the depletion region has negative ions and n-side of the depletion region has positive ions.

When doping is kept high in P-N junction, then there will be less space for electrons to travel.

Depletion width is non linearly and inversely proportional to the doping;

W ∝ 1/(√doping)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 15

List-1 (pole location) with list-2(shown constant amplitude with impulse response).

Select the correct answer using the codes given below.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 15
For A

If we plot A then it is similar to the 4 which is followed by equation K1+K2e-at+K3eat

For B

If we plot B then it is similar to the 1 which is followed by equation (sinat +sinbt) u(t)

For C

If we plot c then it is similar to the 3 which is followed by equation eatsinbt u(t)

For D

If we plot D then it is similar to the 2 which is followed by equation sinat u(t)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 16

For the latch circuit shown below, which of the following options is correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 16

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 17

In a PCM system, if the code word length is increased from 6 to 8 bits, the signal to quantization noise ratio improves by the factor

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 17
When word length is 6

(S/N)N=6 = 22×6 = 212

When word length is 8

(S/N)N=8 = 22×8 =216

now (S/N)N=8/(S/N)N=6 = 216/212 = 24 =16

Thus it improves by a factor of 16.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 18

The far field of an antenna varies with distance r as

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 18
The far field is the region far from the antenna, as you might suspect. In this region, the radiation pattern does not change shape with distance.

Far field is inversely proportional to distance r.

Far field ∝ 1/r

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 19

A semiconductor sample at room temperature has an intrinsic concentration of 2.5 X 1017 /m3. After doping what will be the minority carrier concentration if the majority carrier concentration is given as 5.5 X 1021 /m3.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 19
In a pure Semiconductor (Intrinsic Semiconductor), the electron and hole concentrations are n1p1 respectively. By doping impurity atoms the SC becomes extrinsic then the electrons and hole concentrations n2p2 respectively, then the following equations are acceptable

n1p1 = n2p2 = ni2

For Intrinsic Semiconductor, n=p=ni2 and as per questions before doping n1p1=ni2

Therefore,

p2=ni2n2

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 20

If the block diagram shown in figure 'A' and figure 'B' are equivalent, then x in figure 'B' will be equal to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 20

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 21

For an ideal p-channel MOSFET, μp= 300cm2/v-s, W = 15μm, L = 1.5μm, tox = 300A, Vt = -0.7V. If the transistor is non-saturation region at VSD=0.5V, then what is the Transconductance gm?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 21
ID = (μpCox/2)(W/L)(2(VSG+VT)VSD-VSD2)2 ,

where

Cox = (3.9x85x1014)/(300x1010).

Cox = 1.15x10-7 F/m2. Also, gm =∂(ID)/∂(VSG).

On substituting and solving, gm = 0.172mS.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 22

Which of the following is/are s-domain equivalent of the circuit shown below?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 22
For an inductor, time-domain to s -domain transformation is shown as,

or

For t < 0="" />

i(0) = 10 mA

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 23

From the circuit given below, find out the operating region of the transistors T1 and T2

(VTH = -0.4)

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 23
For T1

VSD = VS – VD = 1.5 – 0 = 1.5 V

VSD(sat)=VSG+VTH=(1.5−0.5)−0.4

= 1 – 0.4 = 0.6V

Here, VSG > (VTH) & VSD > VSD(sat)

So, T1 is in Saturation region

Similarly for T2,

VSD = VS−V0= 0.9−0.9 = 0

VSD(sat)=VSG+VTH= (0.9 − 0) − 0.4 = 0.5V

Here VSDSD(sat) & VSG>(VTH)

∴ T2 in linear region

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 24

Consider the following CT systems with an input x(t) and output y(t).

System P : y(t) = dx(t)/dt

System Q : y(t) = ex(t)

System R : y(t) = 3x(t)

System S : y(t) = 3x(t) + 5

Which of the above system is/are linear?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 24
System P

(System P is linear)

System Q:

(System Q is not linear)

System R:

= ay1(t) + by2(t) (System R is linear)

System S:

(System S is not linear)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 25

A communication channel having AWGN characteristics is operating in such a way that SNR >> 1. The bandwidth of signal being transmitted is B and capacity C1. Determine the capacity of channel if a signal with half the bandwidth is transmitted through the same channel with same quality.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 25
Here same quality implies that SNR for transmitted signals is kept equal. We have a formula for channel capacity as

C1=B1log2⁡(1+S/N)

Now, B2 = 0.5 × B1. SNR is same, thus C2 would be,

C2 = 0.5 * B1log2(1 + S/N) = 0.5 * C1

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 26

In the following scheme, if the spectrum M(f) of m(t) is as shown, then the spectrum Y(f) of y(t) will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 26
The block diagram is as shown below

All waveform is shown below

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 27

An amplifier operating over the frequency range of 18 to 20 MHz has a 10kΩ input resistance.The RMS noise voltage at the input to the amplifier at ambient temperature is (assume Boltzman’s constant = 1.38 × 1023J/K)

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 27

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 28

Consider two functions x = ψ ln Φ and y =Φ In ψ . Which of the following is the correct expression for ∂ψ/∂x ?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 28
x = ψ ln Φ ⇒ ψ = x/ln Φ….(i)

y =Φ In ψ ⇒ Φ = y/In ψ

Putting value of Φ in (i), we get

Assuming y constant and differentiating ψ with respect to x.

Putting value of ( In y - In(In ψ)) = x/ψ from equation (ii) in equation (iii), we get

(Replacing x by Φ in ψ)

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 29

What is the maximum torque (in Nm) on a square loop of 200 turns in a field of uniform flux density of 1 Wb/m2. The loop has 15cm side and carries a current of 5A.


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 29
Max torque, Tmax = NBIS

N-no of turns = 200

B = 1 Wb/m2

I = 5A

S-area of loop = (15x10-2)2 = 0.0225

Tmax = 200×1×5×0.0225 = 22.5Nm

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 30

The sampling rate for Compact Discs (CDs) is 44,000 samples/s. If the samples are quantized to 256 levels and binary coded, the corresponding bit rate (in bits per second) is ______.(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 30
Given,

Sampling Rate = 44,000 Samples / sec

Number of Quantization levels = 256.

No. of Bits required for each sample = log2256 = 8 bits/sample.

This we got under the assumption that all levels are equiprobable.

Thus bit rate = 8 bits/sample X 44,000 Samples/sec = 3,52,000 bits/sec

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 31

The maximum number of Boolean expression that can be formed for the function f(x,y,z) satisfying the relation f(x¯,y,z¯) = f(x,y,z) is


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 31
For every combination of x,y,z the function value remains same for input x¯,y,z¯

Effectively there are only four rows for the truth table of the function f(x,y,z).

Total Boolean expression possible is 24 = 16

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 32

The voltage across and current through a circuit element are, respectively given as,

v(t) = 60 cos(100t + 40°) V

i(t) = 15 cos(100t − 20°) A

The power (in W) absorbed by the element is

(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 32
V = 60∠40o V, I = 15∠-20oA

P = 1/2|V||I|cosθ

= 1/2(60)(15)cos60o

θ = 40o + 20o = 60o

= 1/2(60)(15) x 1/2 = 225 W

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 33

If w = z/(z−i/3)and |w| = 1, then z lies on

where w and z are complex numbers

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 33

⇒ 3|z| = |3z - 1|

Let z = x + iy

⇒ 6y - 1 = 0, I.e. a straight line

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 34

Two 5-bit binary numbers, i.e. X = 01110 and Y = 11001 are represented in two's complement format. The sum of X and Y represented in two's complement format using 6 bits is

(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 34
MSB of Y is 1, thus it is negative number and X is positive number

Now we have X = 01110 = (14)10

and Y = 11001 = (-7)10

X + Y = (14) + (-7) = 7

In signed two’s complements from 7 is

(7)10 = 000111

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 35

In a broadcast super heterodyne receiver the quality factor of antenna coupling circuit is 150, if the intermediate frequency is 455 KHz, then the image rejection ratio at 20 MHz is.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 35
Fsi = fs + 2IF

= 20000 + 455 x 2

= 20910 KHz

ρ = fsi/fs - fs/fsi = 20.910/20 - 20/20.910 = 0.089

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 36

The singular solution of the differential equation y = px + p3, (p = dy/dx) is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 36
We have, y = px + p3 …(i)

Differentiating with respect to x, we get

or (x + 3p2)dp/dx = 0 (since dy/dx = p)

Eliminating p between x + 3p2 = 0 and y = px + p3, we get

or y = 2/3xp

or 9y2 = 4x2(-x/3)

or 27y2 + 4x3 = 0

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 37

A 700 mW maximum power dissipation diode at 25 °C has 5 mW/oC de-rating factor. If the forward voltage drop remains constant at 0.7 V, the maximum forward current at 65 °C is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 37
Power derating factor dW/dt = −5mW/C

So power available at 65oC

= 700mW − 5 × (65 − 25)mW

= (700 - 200)mW = 500mW

Now

P = VI

∴ 500 mW = 0.7 x l

∴ I = 500/0.7 mA = 714 mA

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 38

Match 'List I' with 'List II' and choose the correct option.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 38
For 16/s2, 20log16 – 40logω = 0; ω = √k = 4

For 9/s, 20log9 – 20logω = 0; ω = 9

For 16s2, 20log 16 + 40logω = 0; ω = 1/4

For 9s, 20log 9 + 20log ω = 0; ω = 1/9

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 39

What is the image rejection ratio when a super heterodyne receiver with quality factor of 50 is tuned with fs = 800 KHz and local oscillator frequency is 1250 KHz.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 39
IF = f1 − fs

= 1250 − 800 = 450KHz

fsi = fs + 2IF = 1700KHz

fsi/fs - fs/fsi

IRR = 82.7

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 40

Consider the following statements:

  1. Both ferromagnetic and ferrimagnetic materials have domain structures; each domain has randomly oriented magnetic moments when no external field is applied.

  2. Both ferromagnetic and ferrimagnetic materials make those domains that have favourable orientation to the applied field grow in size.

  3. The net magnetic moment in ferromagnetic material is higher than that in ferrimagnetic material.

  4. The net magnetic moment in ferrimagnetic material is higher than that in ferromagnetic material.

Which of the above statements are correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 40
Ferrimagnetism

The magnetism is a result of the alignment of tiny regions in the material called 'magnetic domains' or 'magnetic moments' in the material. For ferrimagnetism, neighbouring magnetic moments lie in opposite directions. Normally, the opposite ordering cancells out the overall magnetic field of an object; however, in a ferrimagnet, small differences between neighbouring domains make a magnetic field possible.

Ferromagnetism:

Ferromagnetism occurs in some elements such as iron, nickel and cobalt. In these elements, the magnetic moments align in the same direction and parallel to each other to produce strong permanent magnets. Recently, rare earth elements such as neodymium have been found to greatly intensify ferromagnetism, resulting in powerful, compact permanent magnets.

Some magnetic domains in a ferrimagnetic material point in the same direction and some in the opposite direction. However, in ferromagnetism they all point in the same direction. For a ferromagnet and a ferrimagnet of the same size, the ferromagnet will likely have a stronger magnetic field.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 41

A sinusoidal oscillator is built using an amplifier of real gain A, infinite input impedance and the feedback(β) network as shown in the figure.

If Z = jX then Z0 is equal to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 41
Gain without feedback = -AZL/R0 + ZL

For zero phase shift

Z0 + 2 = 0 (As Z0 + 2Z is imaginary)

Z0 = – 2Z = – 2jX

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 42

Match the following and choose the correct option.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 42
ASK signal will be present when '1' is transmitted and absent when '0' is transmitted. Hence, ON – OFF format will be used.

In PSK, for phase reversal a non-return to zero format will be used.

In FSK,

fi (t) = fc (t) + kf Av for '1'

fC (t) – kf AV for '0'

Hence, non-return to zero format will be used.

In DPSK, the output of differential enconder will be in ON – OFF format which is then modified using amplitude level shifting to get NRZ format.

In QPSK,

For '10'

ACcos2πfC t – ACsin2πfCt. Hence, NRZ format is used.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 43

Two 4-ray signal constellations are shoen. It is given that ϕ1and ϕ2constitute an orthonormal basis for the two constellations. Assume that the four symbols in both the constellations are equiprobable. Let N0/2 denote the power spectral density of white Gaussian noise.

The ratio of the average energy of Constellation 1 to the average energy of Constellation 2 is:

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 43
Average energy of constellation 1 is

E1 = (0 + 4a2 + 4a2 + 8a2)/4 = 4a2

Average energy of constellation 2 is

E2 = (a2 + a2 + a2 + a2)/4 = a2

So, E1/E2 = 4a2/a2 = 4

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 44

Two independent random voltage processes x1(t) and x2(t) are applied to an RC network as shown below. If the spectral power density of the two processes are respectively,

then, the output power spectral density will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 44

Because the network is linear, the output voltage y(t) can be expressed as

y(t) = y1(t) + y2(t)

where, y1(t) : HP from input x1 (t) (assuming x2 (t) = 0)

and y2 (t) : HP from input x2 (t) (assuming x1 (t) = 0)

The transfer functions relating y(t) to x1 (t) and x2 (t) are H1and H2, respectively. These are given by

x1(t) and x2(t) are independent. So, the output y1(t) and y2(t) generated by them will also be independent.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 45

In synchronous TDM, there are four inputs and data rate of each input connection is 3 kbps. If 1 bit at a time is multiplexed, what is the duration of each frame?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 45

Given, N = 4n = 1bit fs = 3kbps

bit raterb = n.N.fs = 1 x 4 x 3kbps = 12kbps

Each bit duration = Tb = 1/rb = 1/12kbps = 1/12 X 10-3s = 1/12 ms

Duiration of each frame = 4Tb = 4 x 1/12 ms = 0.333 ms

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 46

The feedback control system represented by the open loop transfer function G(s) H(s) = is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 46
G(s) H(s) =

The characteristic equation is 1 + G(s) H(s) = 0

⇒ (s + 1) (s + 3) (s - 5) + 10 (s + 2) = 0

⇒ s3 - s2 - 7s + 5 = 0

By inspection of characteristic equation, it is clear that system is unstable as all the coefficients of s are not of the same sign.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 47

Silicon is doped with boron to a concentration of 4 × 1017 atoms/cm3. Assuming the intrinsic carrier concentration of silicon to be 1.5×1010/cm3 and the value of kT/q to be 25 mV at 300 K

Compared to undoped silicon, the Fermi level of doped silicon?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 47
E2 – E1 = kTln (NA/ni)

NA = 4×1017

ni = 1.5×1010

E2 – E1 = 25×10-3 e ln 4×1017/1.5×1010 = 0.427eV

Hence Fermi level goes down by 0.427 eV as silicon is doped with boron.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 48

A causal and stable LTI system has the property that

The difference equation for this system relating any input x[n] and the corresponding output y[n] is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 48

Taking inverse Fourier transform, we get

or 3y[n] - 2y[n - 1] = 2x[n - 1]

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 49

Consider the following synchronous counter made up of JK, D and T flip-flops.

Find the modulus value of the counter.


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 49
Consider characteristics equation of J-K flip-flop

if Q0 = 1 ⇒ Q2N − 1 = 0

Consider characteristic equation of D- Flip-Flop : QN+1 = D

QN+1 = Q2….(ii)

Consider characteristics equation of T-Flip-flop: QN+1 = T ⊕ QN

Qx+1 = Q1 ⊕ Q0

Using equations (i), (ii) and (iii)

The number of used states = 5

∴ Modulus value of the counter = 5.

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 50

A phase controlled single phase rectifier, supplied by an AC source, feeds power to an R-L-E load as shown in the figure. The rectifier output voltage has an average value given by ,where Vm = 80π volts and α is the firing angle. If the power delivered to the lossless battery is 1600W, α in degree is ________.(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 50
Power delivered to lossless battery = EI0 = 1600W

80I0 = 1600

I0 = 20 A

From given 1 - Φ rectifier, V0 = E + I0R

40[3 + cosα] = 120

3 + cos α = 3

cos α = 0

α = 90o

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 51

Following the state diagram shown clocked sequential circuit:

How many states the sequential circuit has?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 51

Drawing a state table: (Let input be X)

State e and g are equivalent because the next states and outputs are same. We can eliminate any one them, say ‘g’. Thus ‘g’ is replaced by ‘e’ wherever it occurs. Now sated d and f are equivalent. Thus one of them say d, can be eliminated. Thus the reduced state table-

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 52

Consider the following 8085 microprocessor program.

LDA 4200 H

CMA

ADI 01 H

STA 4300 H

HLT

If the memory content of 4200 H is 77 H, then the memory content of 4300 H will be -----H.

(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 52
Perform 2's complement,

A← 4200 H

A ← 77 H

CMA → 77 H →10001000→ 88 H

So, 4300 ← 89 H

If the memory content of 4200 H is 77 H, then the memory content of 4300 H will be 89 H.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 53

Find by double integration the volume of the solid generated by revolving the ellipse

x2/a2 + y2/b2 = 1 about the x-axis.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 53
Here we shall consider the revolution of the only upper half of the ellipse about the x-axis , because volumes generated by upper and lower halves overlap. If V is the required volume, then

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 54

Consider the amplitude modulated (AM) signal Ac cos ωct + 2 cosωm t cosωct . For demodulating the signal using envelope detector, the minimum value of Ac should be

(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 54
We have xAM = Ac cos ωct + 2 cosωm t cosωct

For demodulation by envelope demodulator modulation index must be less than or equal to 1.

Thus 2/Ac ≤ 1

Ac ≥ 2

Hence minimum value of Ac = 2

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 55

Consider the following differential equation dy/dx = −x+1

If y (2) = 1 then the value of y (2.2) using Runge- Kutta third order method is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 55
here, f(x) = −x + 1

h = 0.2,x0 = 2,y0 = 1

According to Runge-Kutta third order method

y1 = y0 + 16[K1 + 4K2 + K3]

Where,

K1 = hf(x0,y0) = hf(2,1)

= 0.2 × (−2 + 1) = −0.2

K2 = hf(x0 + h/2, y0 + h/2) = hf(2 + 0.2/2,1 + 0.2/2)

= 0.2 × f(2.1,1.1)

= 0.2 × (−2.1 + 1)

= −0.22

K3 = hf(x0 + h,y0 + 2K2 − K1)

= hf(2 + 0.2,1 + 2 × (−0.22) + 0.2)

= 0.2 × f(2.2,0.76)

= 0.2 × (−2.2 + 1)

= −0.24

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 56

The equivalent inductance of the circuit shown in the figure is equal to ___ H. (Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 56
For coil 1, L1eq = L1 – M12 + M13

= 7 – 3 + 1 = 5 H (M12 = 3 H, M13 = 1 H)

L2eq = L2 – M21 – M23

= 9 – 3 – 4 = 2 H (M23 = 4 H)

L3eq = L3 + M31 – M32

= 11 + 1 – 4 H = 8 H

Leq = L1eq + L2eq + L3eq = 5 + 2 + 8 = 15 H

Alternatively:

Leq = L1 + L2 + L3 – 2M12 – 2M23 + 2M13

= 7 + 9 + 11 – 2(3) – 2(4) + 2(1)

= 27 – 6 – 8 + 2 = 15 H

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 57

Consider the two port network shown below

If Vo(s)/V1(s) = s3/(s3 + 6s + 12s + 24) then C2 is _______ F.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 57

From here, 1/C1L = 12 1/LC1C2 = 24

C2 = 0.5F

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 58

In the circuit shown below, the emitter current is 26 μA. What will be the value of input impedance (in kΩ )? (Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 58
Zi = 1kΩ || re

re = 26 mV/IE = 26mV/26 μA = 1kΩ

zi = 1 kΩ || 1kΩ = 0.5 kΩ

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 59

For the opamp biasing shown in figure, it was found experimentally even at zero bias the current flowing into positive terminal is 15nA and current flowing into negative terminal is 10nA. If the output voltage of op-amp is 8mV. The value of feedback resistance Rf is__________.

Assume (Rf≫ R). R = 0.5 kΩ

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 59
Assuming ideal op-amp and Rf≫ R current can be modelled as voltage source

I+ = current at positive non-inverting terminal

I- = current at the negative inverting terminal

Vo+ = output voltage due to non-inverting current flow

Vo- = output voltage due to non-inverting current flow

(Taking inverting node ground)

= I+R + I+Rf

Vo = IR(−Rf/R)

V0 (offset) = V0+ + V0 (By superposition theorem)

= I+R + I+Rf − IRf

= I+R + Rf(l+ − I)

8mV = 15 × 0.5 × 10−16 + Rf(15 − 10) × 10−9

(8×10−3−7.5×10−6)/5×10−9 = Rf

Rf ≈ 1.6 M Ω

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 60

A buck converter that feeds a variable resistive load is shown in the figure. The switching frequency of the switch S is 100 kHz and the duty ratio is 0.6. The output voltage V0 is 36 V. Assume that all the components are ideal and the output voltage is ripple-free. The value of R (in Ohm) that will make the inductor current (iL) just continuous is (Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 60

Given circuit is

Also, we have

fo = 100 kHz

Duty cycle = 0.6

Vo = 36 V

When switch is ON, then

Vs = Vo + Ldi/dt or Ldi/dt = Vs - Vo

At critical value, ∆IL = I0/2, we have

Hence, R = 1250 Ω

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 61

The Fourier transform of continuous time signal X(t) = 3cos(10t) + 4sin(10t) is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 61
x(t) = 3cos(10t) + 4sin(10t)

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 62

Consider the circuit shown in the figure below. The voltage V across the load is measured by taking three different values of load (ZL) and given in the table below.

The magnitude of Thevenin voltage (in V) for the circuit shown in the box is equal to _____. (Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 62

|vTh| = 230.5 V

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 63

Find the systems response to the input x[n] = u[n]| if the unit impulse response h[n] of a DT LTI system is h[n] = ?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 63
Given

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 64

For a JFET, the following readings were obtained experimentally:

What is the amplification factor (α) of the JFET?

(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 64
α = rd x gm

rd = ΔVds/ΔID

With VGS = 0 V constant, VDS increases from 7 V to 15 V, ID changes from 10 mA to 10.25 mA.

ΔVds = 8 V

ΔID = 0.25 mA

rd = 8/0.25 m = 32 kΩ

α = 32 x 103 x 3 x 10–3 = 96

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 65

Find the capacitor voltage VC at t = 1msec if switch is closed as t = 0. Assume capacitor initially uncharged and op-amp is not saturated.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 65

I = (0 - 10)/2K = -5mA

Vc = 1/CഽIdt

= [1 / (2 x 10-6)]ഽ- 5mAdt

= [ -5m/(2 x 10-6)] x t

VC = -2.5 x 103 1msec

VC = -2.5 V

24 docs|263 tests
Information about GATE Mock Test Electronics Engineering (ECE)- 3 Page
In this test you can find the Exam questions for GATE Mock Test Electronics Engineering (ECE)- 3 solved & explained in the simplest way possible. Besides giving Questions and answers for GATE Mock Test Electronics Engineering (ECE)- 3, EduRev gives you an ample number of Online tests for practice

Up next

Download as PDF

Up next

Download the FREE EduRev App
Track your progress, build streaks, highlight & save important lessons and more!