Analog & DE - MCQ Test 1


10 Questions MCQ Test Mock Test Series for Electrical Engineering (EE) GATE 2020 | Analog & DE - MCQ Test 1


Description
This mock test of Analog & DE - MCQ Test 1 for GATE helps you for every GATE entrance exam. This contains 10 Multiple Choice Questions for GATE Analog & DE - MCQ Test 1 (mcq) to study with solutions a complete question bank. The solved questions answers in this Analog & DE - MCQ Test 1 quiz give you a good mix of easy questions and tough questions. GATE students definitely take this Analog & DE - MCQ Test 1 exercise for a better result in the exam. You can find other Analog & DE - MCQ Test 1 extra questions, long questions & short questions for GATE on EduRev as well by searching above.
QUESTION: 1

A voltage V = 4 sin ωt is applied to the terminals A and B of the circuit shown in figure. The diodes are assumed to be ideal. The impedance offered by the circuit across the terminals A and B in kilo-ohms is

Solution:
QUESTION: 2

Consider the following limiter circuit an input voltage V| = 10.5 sinlOOnt is applied. Assume that the diode drop is 0.7 V in forward bias. The zener breakdown voltage is 6.3 V.

The maximum and minimum values of the output voltage respectively are

Solution:

For +ve value of Vi, D1 is F.B and zener diode regulates the voltage at 6.3 V across it.
V0 = 6.3 + 0.7 = 7 V
and for negative half of V:, D2 is forward biased.
'    V0 = -0.7 V

QUESTION: 3

In the saturation region of a BJT (Bipolar Junction Transistor)

Solution:

Both junctions could be forward biased.

QUESTION: 4

Given below is the Ic Vs VCE characteristic of two npn transistor P and Q having current gains β1 and β2 respectively.

Hard lines: Characteristics of P Dashed lines: Characteristics of Q

Which of the following is true?

Solution:

β of Q should be >> β of P.

QUESTION: 5

The thermal run-away in a CE-transistor amplifier can be prevented by biasing in such a wav that.

Solution:

It is derived from the basic condition.

QUESTION: 6

IDSS = 8 mA Vp = -5 V, Assume Gate current » 0 all the capacitance used are of very large value. The voltage gain Av, is

Solution:

QUESTION: 7

If the differential voltage gain and the common mode voltage gain of a differential amplifier are 50-dB and 2-dB resDectivelv. then its common mode rejection ratio is

Solution:

QUESTION: 8

Consider the following op-amp circuit:

Op-amp slew rate is SR = 0.5 V/μsec.

Maximum frequency where the op-amp can operate is

Solution:

QUESTION: 9

Consider the following op-amp circuit with multiple stages:

Solution:

I0 = kIi (current controlled current source).

QUESTION: 10

Shown below is a positive feedback arrangement to generate sinusoidal oscillation 

 

Solution:

 

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